1*4882a593Smuzhiyun* Rockchip Rk3228 internal codec 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: "rockchip,rk3228-codec" 6*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 7*4882a593Smuzhiyun region. 8*4882a593Smuzhiyun- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. 9*4882a593Smuzhiyun- clock-names: a list of clock names, one for each entry in clocks. 10*4882a593Smuzhiyun- spk-en-gpio: speaker enable gpio. 11*4882a593Smuzhiyun- spk-depop-time-ms: speaker depop time msec. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample for rk3228 internal codec: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyuncodec: codec@12010000 { 16*4882a593Smuzhiyun compatible = "rockchip,rk3228-codec"; 17*4882a593Smuzhiyun reg = <0x12010000 0x1000>; 18*4882a593Smuzhiyun clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 19*4882a593Smuzhiyun clock-names = "mclk", "pclk", "sclk"; 20*4882a593Smuzhiyun spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 21*4882a593Smuzhiyun status = "disabled"; 22*4882a593Smuzhiyun}; 23