1*4882a593Smuzhiyun* Rockchip SPDIF Receiver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe S/PDIF audio block is a stereo receiver that allows the 4*4882a593Smuzhiyunprocessor to receive and digital audio via an coaxial cable or 5*4882a593Smuzhiyuna fibre cable. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: should be one of the following: 10*4882a593Smuzhiyun - "rockchip,rk3308-spdifrx" 11*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 12*4882a593Smuzhiyun region. 13*4882a593Smuzhiyun- interrupts: should contain the SPDIF interrupt. 14*4882a593Smuzhiyun- dmas: DMA specifiers for rx dma. See the DMA client binding, 15*4882a593Smuzhiyun Documentation/devicetree/bindings/dma/dma.txt 16*4882a593Smuzhiyun- dma-names: should be "rx" 17*4882a593Smuzhiyun- clocks: a list of phandle + clock-specifier pairs, one for each entry 18*4882a593Smuzhiyun in clock-names. 19*4882a593Smuzhiyun- clock-names: should contain following: 20*4882a593Smuzhiyun - "hclk": clock for SPDIF controller 21*4882a593Smuzhiyun - "mclk" : clock for SPDIF bus 22*4882a593Smuzhiyun- resets: a list of phandle + reset-specifer paris, one for each entry in reset-names. 23*4882a593Smuzhiyun- reset-names: reset names, should include "spdifrx-m". 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample for the rk3308 SPDIF-RX controller: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunspdif_rx: spdif-rx@ff3b0000 { 28*4882a593Smuzhiyun compatible = "rockchip,rk3308-spdifrx"; 29*4882a593Smuzhiyun reg = <0x0 0xff3b0000 0x0 0x1000>; 30*4882a593Smuzhiyun interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 31*4882a593Smuzhiyun clocks = <&cru SCLK_SPDIF_RX>, <&cru HCLK_SPDIFRX>; 32*4882a593Smuzhiyun clock-names = "mclk", "hclk"; 33*4882a593Smuzhiyun dmas = <&dmac1 14>; 34*4882a593Smuzhiyun dma-names = "rx"; 35*4882a593Smuzhiyun resets = <&cru SRST_SPDIFRX_M>; 36*4882a593Smuzhiyun reset-names = "spdifrx-m"; 37*4882a593Smuzhiyun status = "disabled"; 38*4882a593Smuzhiyun}; 39