1* Rockchip Codec Digital Interface 2 3Required properties: 4 5- compatible: should be one of the following 6 - "rockchip,codec-digital-v1" 7 - "rockchip,rk3568-codec-digital" 8 - "rockchip,rk3588-codec-digital" 9 - "rockchip,rv1106-codec-digital" 10 - "rockchip,rv1126-codec-digital" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. 14- clock-names: clock names. 15- rockchip,bclk-fs: configure the bclk fs. 16- resets: a list of phandle + reset-specifer paris, one for each entry in reset-names. 17- reset-names: reset names, should include "reset". 18- rockchip,grf: the phandle of the syscon node for GRF register. 19 20Optional properties: 21- rockchip,clk-sync-mode: This is a boolean property, if present, using clk 22 sync mode. 23- rockchip,pwm-output-mode: This is a boolean property, if present, output pwm 24 to drive spk. 25 26Example: 27 28rkacdc_dig: codec-digital@ff850000 { 29 compatible = "rockchip,codec-digital-v1"; 30 reg = <0xff850000 0x1000>; 31 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, 32 <&cru PCLK_ACDCDIG>; 33 clock-names = "adc", "dac", "pclk"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&acodec_pins>; 36 resets = <&cru SRST_ACDCDIG>; 37 reset-names = "reset" ; 38 rockchip,grf = <&grf>; 39 status = "disabled"; 40}; 41