1*4882a593SmuzhiyunNVIDIA Tegra30 AHUB (Audio Hub) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114, 5*4882a593Smuzhiyun must contain "nvidia,tegra114-ahub". For Tegra124, must contain 6*4882a593Smuzhiyun "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub", 7*4882a593Smuzhiyun plus at least one of the above, where <chip> is tegra132. 8*4882a593Smuzhiyun- reg : Should contain the register physical address and length for each of 9*4882a593Smuzhiyun the AHUB's register blocks. 10*4882a593Smuzhiyun - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. 11*4882a593Smuzhiyun - Tegra114 requires an additional entry, for the APBIF2 register block. 12*4882a593Smuzhiyun- interrupts : Should contain AHUB interrupt 13*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 14*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 15*4882a593Smuzhiyun- clock-names : Must include the following entries: 16*4882a593Smuzhiyun - d_audio 17*4882a593Smuzhiyun - apbif 18*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 19*4882a593Smuzhiyun See ../reset/reset.txt for details. 20*4882a593Smuzhiyun- reset-names : Must include the following entries: 21*4882a593Smuzhiyun Tegra30 and later: 22*4882a593Smuzhiyun - d_audio 23*4882a593Smuzhiyun - apbif 24*4882a593Smuzhiyun - i2s0 25*4882a593Smuzhiyun - i2s1 26*4882a593Smuzhiyun - i2s2 27*4882a593Smuzhiyun - i2s3 28*4882a593Smuzhiyun - i2s4 29*4882a593Smuzhiyun - dam0 30*4882a593Smuzhiyun - dam1 31*4882a593Smuzhiyun - dam2 32*4882a593Smuzhiyun - spdif 33*4882a593Smuzhiyun Tegra114 and later additionally require: 34*4882a593Smuzhiyun - amx 35*4882a593Smuzhiyun - adx 36*4882a593Smuzhiyun Tegra124 and later additionally require: 37*4882a593Smuzhiyun - amx1 38*4882a593Smuzhiyun - adx1 39*4882a593Smuzhiyun - afc0 40*4882a593Smuzhiyun - afc1 41*4882a593Smuzhiyun - afc2 42*4882a593Smuzhiyun - afc3 43*4882a593Smuzhiyun - afc4 44*4882a593Smuzhiyun - afc5 45*4882a593Smuzhiyun- ranges : The bus address mapping for the configlink register bus. 46*4882a593Smuzhiyun Can be empty since the mapping is 1:1. 47*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in clock-names. 48*4882a593Smuzhiyun See ../dma/dma.txt for details. 49*4882a593Smuzhiyun- dma-names : Must include the following entries: 50*4882a593Smuzhiyun - rx0 .. rx<n> 51*4882a593Smuzhiyun - tx0 .. tx<n> 52*4882a593Smuzhiyun ... where n is: 53*4882a593Smuzhiyun Tegra30: 3 54*4882a593Smuzhiyun Tegra114, Tegra124: 9 55*4882a593Smuzhiyun- #address-cells : For the configlink bus. Should be <1>; 56*4882a593Smuzhiyun- #size-cells : For the configlink bus. Should be <1>. 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunAHUB client modules need to specify the IDs of their CIFs (Client InterFaces). 59*4882a593SmuzhiyunFor RX CIFs, the numbers indicate the register number within AHUB routing 60*4882a593Smuzhiyunregister space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). 61*4882a593SmuzhiyunFor TX CIFs, the numbers indicate the bit position within the AHUB routing 62*4882a593Smuzhiyunregisters (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunExample: 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunahub@70080000 { 67*4882a593Smuzhiyun compatible = "nvidia,tegra30-ahub"; 68*4882a593Smuzhiyun reg = <0x70080000 0x200 0x70080200 0x100>; 69*4882a593Smuzhiyun interrupts = < 0 103 0x04 >; 70*4882a593Smuzhiyun nvidia,dma-request-selector = <&apbdma 1>; 71*4882a593Smuzhiyun clocks = <&tegra_car 106>, <&tegra_car 107>; 72*4882a593Smuzhiyun clock-names = "d_audio", "apbif"; 73*4882a593Smuzhiyun resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, 74*4882a593Smuzhiyun <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, 75*4882a593Smuzhiyun <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, 76*4882a593Smuzhiyun <&tegra_car 110>, <&tegra_car 10>; 77*4882a593Smuzhiyun reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 78*4882a593Smuzhiyun "i2s3", "i2s4", "dam0", "dam1", "dam2", 79*4882a593Smuzhiyun "spdif"; 80*4882a593Smuzhiyun dmas = <&apbdma 1>, <&apbdma 1>; 81*4882a593Smuzhiyun <&apbdma 2>, <&apbdma 2>; 82*4882a593Smuzhiyun <&apbdma 3>, <&apbdma 3>; 83*4882a593Smuzhiyun <&apbdma 4>, <&apbdma 4>; 84*4882a593Smuzhiyun dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3"; 85*4882a593Smuzhiyun ranges; 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <1>; 88*4882a593Smuzhiyun}; 89