1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Tegra210 AHUB Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun The Audio Hub (AHUB) comprises a collection of hardware accelerators 11*4882a593Smuzhiyun for audio pre-processing, post-processing and a programmable full 12*4882a593Smuzhiyun crossbar for routing audio data across these accelerators. It has 13*4882a593Smuzhiyun external interfaces such as I2S, DMIC, DSPK. It interfaces with ADMA 14*4882a593Smuzhiyun engine through ADMAIF. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunmaintainers: 17*4882a593Smuzhiyun - Jon Hunter <jonathanh@nvidia.com> 18*4882a593Smuzhiyun - Sameer Pujar <spujar@nvidia.com> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun $nodename: 22*4882a593Smuzhiyun pattern: "^ahub@[0-9a-f]*$" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun oneOf: 26*4882a593Smuzhiyun - enum: 27*4882a593Smuzhiyun - nvidia,tegra210-ahub 28*4882a593Smuzhiyun - nvidia,tegra186-ahub 29*4882a593Smuzhiyun - items: 30*4882a593Smuzhiyun - const: nvidia,tegra194-ahub 31*4882a593Smuzhiyun - const: nvidia,tegra186-ahub 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-names: 40*4882a593Smuzhiyun const: ahub 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun assigned-clocks: 43*4882a593Smuzhiyun maxItems: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun assigned-clock-parents: 46*4882a593Smuzhiyun maxItems: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun assigned-clock-rates: 49*4882a593Smuzhiyun maxItems: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun "#address-cells": 52*4882a593Smuzhiyun const: 1 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun "#size-cells": 55*4882a593Smuzhiyun const: 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ranges: true 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunrequired: 60*4882a593Smuzhiyun - compatible 61*4882a593Smuzhiyun - reg 62*4882a593Smuzhiyun - clocks 63*4882a593Smuzhiyun - clock-names 64*4882a593Smuzhiyun - assigned-clocks 65*4882a593Smuzhiyun - assigned-clock-parents 66*4882a593Smuzhiyun - "#address-cells" 67*4882a593Smuzhiyun - "#size-cells" 68*4882a593Smuzhiyun - ranges 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunadditionalProperties: 71*4882a593Smuzhiyun type: object 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunexamples: 74*4882a593Smuzhiyun - | 75*4882a593Smuzhiyun #include<dt-bindings/clock/tegra210-car.h> 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun ahub@702d0800 { 78*4882a593Smuzhiyun compatible = "nvidia,tegra210-ahub"; 79*4882a593Smuzhiyun reg = <0x702d0800 0x800>; 80*4882a593Smuzhiyun clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 81*4882a593Smuzhiyun clock-names = "ahub"; 82*4882a593Smuzhiyun assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 83*4882a593Smuzhiyun assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <1>; 86*4882a593Smuzhiyun ranges = <0x702d0000 0x702d0000 0x0000e400>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun // All AHUB child nodes below 89*4882a593Smuzhiyun admaif@702d0000 { 90*4882a593Smuzhiyun compatible = "nvidia,tegra210-admaif"; 91*4882a593Smuzhiyun reg = <0x702d0000 0x800>; 92*4882a593Smuzhiyun dmas = <&adma 1>, <&adma 1>, 93*4882a593Smuzhiyun <&adma 2>, <&adma 2>, 94*4882a593Smuzhiyun <&adma 3>, <&adma 3>, 95*4882a593Smuzhiyun <&adma 4>, <&adma 4>, 96*4882a593Smuzhiyun <&adma 5>, <&adma 5>, 97*4882a593Smuzhiyun <&adma 6>, <&adma 6>, 98*4882a593Smuzhiyun <&adma 7>, <&adma 7>, 99*4882a593Smuzhiyun <&adma 8>, <&adma 8>, 100*4882a593Smuzhiyun <&adma 9>, <&adma 9>, 101*4882a593Smuzhiyun <&adma 10>, <&adma 10>; 102*4882a593Smuzhiyun dma-names = "rx1", "tx1", 103*4882a593Smuzhiyun "rx2", "tx2", 104*4882a593Smuzhiyun "rx3", "tx3", 105*4882a593Smuzhiyun "rx4", "tx4", 106*4882a593Smuzhiyun "rx5", "tx5", 107*4882a593Smuzhiyun "rx6", "tx6", 108*4882a593Smuzhiyun "rx7", "tx7", 109*4882a593Smuzhiyun "rx8", "tx8", 110*4882a593Smuzhiyun "rx9", "tx9", 111*4882a593Smuzhiyun "rx10", "tx10"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun i2s@702d1000 { 115*4882a593Smuzhiyun compatible = "nvidia,tegra210-i2s"; 116*4882a593Smuzhiyun reg = <0x702d1000 0x100>; 117*4882a593Smuzhiyun clocks = <&tegra_car TEGRA210_CLK_I2S0>; 118*4882a593Smuzhiyun clock-names = "i2s"; 119*4882a593Smuzhiyun assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 120*4882a593Smuzhiyun assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 121*4882a593Smuzhiyun assigned-clock-rates = <1536000>; 122*4882a593Smuzhiyun sound-name-prefix = "I2S1"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun dmic@702d4000 { 126*4882a593Smuzhiyun compatible = "nvidia,tegra210-dmic"; 127*4882a593Smuzhiyun reg = <0x702d4000 0x100>; 128*4882a593Smuzhiyun clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 129*4882a593Smuzhiyun clock-names = "dmic"; 130*4882a593Smuzhiyun assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 131*4882a593Smuzhiyun assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 132*4882a593Smuzhiyun assigned-clock-rates = <3072000>; 133*4882a593Smuzhiyun sound-name-prefix = "DMIC1"; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun // More child nodes to follow 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun... 140