1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Tegra210 ADMAIF Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun ADMAIF is the interface between ADMA and AHUB. Each ADMA channel 11*4882a593Smuzhiyun that sends/receives data to/from AHUB must interface through an 12*4882a593Smuzhiyun ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF 13*4882a593Smuzhiyun Tx channel and ADMA channel receiving data from AHUB pairs with 14*4882a593Smuzhiyun ADMAIF Rx channel. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunmaintainers: 17*4882a593Smuzhiyun - Jon Hunter <jonathanh@nvidia.com> 18*4882a593Smuzhiyun - Sameer Pujar <spujar@nvidia.com> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun $nodename: 22*4882a593Smuzhiyun pattern: "^admaif@[0-9a-f]*$" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun oneOf: 26*4882a593Smuzhiyun - enum: 27*4882a593Smuzhiyun - nvidia,tegra210-admaif 28*4882a593Smuzhiyun - nvidia,tegra186-admaif 29*4882a593Smuzhiyun - items: 30*4882a593Smuzhiyun - const: nvidia,tegra194-admaif 31*4882a593Smuzhiyun - const: nvidia,tegra186-admaif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun dmas: true 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun dma-names: true 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunif: 41*4882a593Smuzhiyun properties: 42*4882a593Smuzhiyun compatible: 43*4882a593Smuzhiyun contains: 44*4882a593Smuzhiyun const: nvidia,tegra210-admaif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunthen: 47*4882a593Smuzhiyun properties: 48*4882a593Smuzhiyun dmas: 49*4882a593Smuzhiyun description: 50*4882a593Smuzhiyun DMA channel specifiers, equally divided for Tx and Rx. 51*4882a593Smuzhiyun minItems: 1 52*4882a593Smuzhiyun maxItems: 20 53*4882a593Smuzhiyun dma-names: 54*4882a593Smuzhiyun items: 55*4882a593Smuzhiyun pattern: "^[rt]x(10|[1-9])$" 56*4882a593Smuzhiyun description: 57*4882a593Smuzhiyun Should be "rx1", "rx2" ... "rx10" for DMA Rx channel 58*4882a593Smuzhiyun Should be "tx1", "tx2" ... "tx10" for DMA Tx channel 59*4882a593Smuzhiyun minItems: 1 60*4882a593Smuzhiyun maxItems: 20 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunelse: 63*4882a593Smuzhiyun properties: 64*4882a593Smuzhiyun dmas: 65*4882a593Smuzhiyun description: 66*4882a593Smuzhiyun DMA channel specifiers, equally divided for Tx and Rx. 67*4882a593Smuzhiyun minItems: 1 68*4882a593Smuzhiyun maxItems: 40 69*4882a593Smuzhiyun dma-names: 70*4882a593Smuzhiyun items: 71*4882a593Smuzhiyun pattern: "^[rt]x(1[0-9]|[1-9]|20)$" 72*4882a593Smuzhiyun description: 73*4882a593Smuzhiyun Should be "rx1", "rx2" ... "rx20" for DMA Rx channel 74*4882a593Smuzhiyun Should be "tx1", "tx2" ... "tx20" for DMA Tx channel 75*4882a593Smuzhiyun minItems: 1 76*4882a593Smuzhiyun maxItems: 40 77*4882a593Smuzhiyun 78*4882a593Smuzhiyunrequired: 79*4882a593Smuzhiyun - compatible 80*4882a593Smuzhiyun - reg 81*4882a593Smuzhiyun - dmas 82*4882a593Smuzhiyun - dma-names 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunadditionalProperties: false 85*4882a593Smuzhiyun 86*4882a593Smuzhiyunexamples: 87*4882a593Smuzhiyun - | 88*4882a593Smuzhiyun admaif@702d0000 { 89*4882a593Smuzhiyun compatible = "nvidia,tegra210-admaif"; 90*4882a593Smuzhiyun reg = <0x702d0000 0x800>; 91*4882a593Smuzhiyun dmas = <&adma 1>, <&adma 1>, 92*4882a593Smuzhiyun <&adma 2>, <&adma 2>, 93*4882a593Smuzhiyun <&adma 3>, <&adma 3>, 94*4882a593Smuzhiyun <&adma 4>, <&adma 4>, 95*4882a593Smuzhiyun <&adma 5>, <&adma 5>, 96*4882a593Smuzhiyun <&adma 6>, <&adma 6>, 97*4882a593Smuzhiyun <&adma 7>, <&adma 7>, 98*4882a593Smuzhiyun <&adma 8>, <&adma 8>, 99*4882a593Smuzhiyun <&adma 9>, <&adma 9>, 100*4882a593Smuzhiyun <&adma 10>, <&adma 10>; 101*4882a593Smuzhiyun dma-names = "rx1", "tx1", 102*4882a593Smuzhiyun "rx2", "tx2", 103*4882a593Smuzhiyun "rx3", "tx3", 104*4882a593Smuzhiyun "rx4", "tx4", 105*4882a593Smuzhiyun "rx5", "tx5", 106*4882a593Smuzhiyun "rx6", "tx6", 107*4882a593Smuzhiyun "rx7", "tx7", 108*4882a593Smuzhiyun "rx8", "tx8", 109*4882a593Smuzhiyun "rx9", "tx9", 110*4882a593Smuzhiyun "rx10", "tx10"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun... 114