1*4882a593SmuzhiyunNVIDIA Tegra 20 I2S controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "nvidia,tegra20-i2s" 5*4882a593Smuzhiyun- reg : Should contain I2S registers location and length 6*4882a593Smuzhiyun- interrupts : Should contain I2S interrupt 7*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 8*4882a593Smuzhiyun See ../reset/reset.txt for details. 9*4882a593Smuzhiyun- reset-names : Must include the following entries: 10*4882a593Smuzhiyun - i2s 11*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in clock-names. 12*4882a593Smuzhiyun See ../dma/dma.txt for details. 13*4882a593Smuzhiyun- dma-names : Must include the following entries: 14*4882a593Smuzhiyun - rx 15*4882a593Smuzhiyun - tx 16*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 17*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyuni2s@70002800 { 22*4882a593Smuzhiyun compatible = "nvidia,tegra20-i2s"; 23*4882a593Smuzhiyun reg = <0x70002800 0x200>; 24*4882a593Smuzhiyun interrupts = < 45 >; 25*4882a593Smuzhiyun clocks = <&tegra_car 11>; 26*4882a593Smuzhiyun resets = <&tegra_car 11>; 27*4882a593Smuzhiyun reset-names = "i2s"; 28*4882a593Smuzhiyun dmas = <&apbdma 21>, <&apbdma 21>; 29*4882a593Smuzhiyun dma-names = "rx", "tx"; 30*4882a593Smuzhiyun}; 31