1*4882a593SmuzhiyunNVIDIA Tegra 20 AC97 controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "nvidia,tegra20-ac97" 5*4882a593Smuzhiyun- reg : Should contain AC97 controller registers location and length 6*4882a593Smuzhiyun- interrupts : Should contain AC97 interrupt 7*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 8*4882a593Smuzhiyun See ../reset/reset.txt for details. 9*4882a593Smuzhiyun- reset-names : Must include the following entries: 10*4882a593Smuzhiyun - ac97 11*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in clock-names. 12*4882a593Smuzhiyun See ../dma/dma.txt for details. 13*4882a593Smuzhiyun- dma-names : Must include the following entries: 14*4882a593Smuzhiyun - rx 15*4882a593Smuzhiyun - tx 16*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 17*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 18*4882a593Smuzhiyun- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number 19*4882a593Smuzhiyun of the GPIO used to reset the external AC97 codec 20*4882a593Smuzhiyun- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number 21*4882a593Smuzhiyun of the GPIO corresponding with the AC97 DAP _FS line 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunac97@70002000 { 26*4882a593Smuzhiyun compatible = "nvidia,tegra20-ac97"; 27*4882a593Smuzhiyun reg = <0x70002000 0x200>; 28*4882a593Smuzhiyun interrupts = <0 81 0x04>; 29*4882a593Smuzhiyun nvidia,codec-reset-gpio = <&gpio 170 0>; 30*4882a593Smuzhiyun nvidia,codec-sync-gpio = <&gpio 120 0>; 31*4882a593Smuzhiyun clocks = <&tegra_car 3>; 32*4882a593Smuzhiyun resets = <&tegra_car 3>; 33*4882a593Smuzhiyun reset-names = "ac97"; 34*4882a593Smuzhiyun dmas = <&apbdma 12>, <&apbdma 12>; 35*4882a593Smuzhiyun dma-names = "rx", "tx"; 36*4882a593Smuzhiyun}; 37