1*4882a593SmuzhiyunNVIDIA Tegra audio complex, with SGTL5000 CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "nvidia,tegra-audio-sgtl5000" 5*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 6*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 7*4882a593Smuzhiyun- clock-names : Must include the following entries: 8*4882a593Smuzhiyun - pll_a 9*4882a593Smuzhiyun - pll_a_out0 10*4882a593Smuzhiyun - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 11*4882a593Smuzhiyun- nvidia,model : The user-visible name of this sound complex. 12*4882a593Smuzhiyun- nvidia,audio-routing : A list of the connections between audio components. 13*4882a593Smuzhiyun Each entry is a pair of strings, the first being the connection's sink, 14*4882a593Smuzhiyun the second being the connection's source. Valid names for sources and 15*4882a593Smuzhiyun sinks are the SGTL5000's pins (as documented in its binding), and the jacks 16*4882a593Smuzhiyun on the board: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun * Headphone Jack 19*4882a593Smuzhiyun * Line In Jack 20*4882a593Smuzhiyun * Mic Jack 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's 23*4882a593Smuzhiyun connected to the CODEC. 24*4882a593Smuzhiyun- nvidia,audio-codec : The phandle of the SGTL5000 audio codec. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunsound { 29*4882a593Smuzhiyun compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", 30*4882a593Smuzhiyun "nvidia,tegra-audio-sgtl5000"; 31*4882a593Smuzhiyun nvidia,model = "Toradex Apalis T30"; 32*4882a593Smuzhiyun nvidia,audio-routing = 33*4882a593Smuzhiyun "Headphone Jack", "HP_OUT", 34*4882a593Smuzhiyun "LINE_IN", "Line In Jack", 35*4882a593Smuzhiyun "MIC_IN", "Mic Jack"; 36*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s2>; 37*4882a593Smuzhiyun nvidia,audio-codec = <&sgtl5000>; 38*4882a593Smuzhiyun clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 39*4882a593Smuzhiyun <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 40*4882a593Smuzhiyun <&tegra_car TEGRA30_CLK_EXTERN1>; 41*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 42*4882a593Smuzhiyun}; 43