1*4882a593SmuzhiyunNVIDIA Tegra30 I2S controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124, 5*4882a593Smuzhiyun must contain "nvidia,tegra124-i2s". Otherwise, must contain 6*4882a593Smuzhiyun "nvidia,<chip>-i2s" plus at least one of the above, where <chip> is 7*4882a593Smuzhiyun tegra114 or tegra132. 8*4882a593Smuzhiyun- reg : Should contain I2S registers location and length 9*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 10*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 11*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 12*4882a593Smuzhiyun See ../reset/reset.txt for details. 13*4882a593Smuzhiyun- reset-names : Must include the following entries: 14*4882a593Smuzhiyun - i2s 15*4882a593Smuzhiyun- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) 16*4882a593Smuzhiyun first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyuni2s@70080300 { 21*4882a593Smuzhiyun compatible = "nvidia,tegra30-i2s"; 22*4882a593Smuzhiyun reg = <0x70080300 0x100>; 23*4882a593Smuzhiyun nvidia,ahub-cif-ids = <4 4>; 24*4882a593Smuzhiyun clocks = <&tegra_car 11>; 25*4882a593Smuzhiyun resets = <&tegra_car 11>; 26*4882a593Smuzhiyun reset-names = "i2s"; 27*4882a593Smuzhiyun}; 28