1*4882a593Smuzhiyun* Microchip I2S Multi-Channel Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "microchip,sam9x60-i2smcc". 5*4882a593Smuzhiyun- reg: Should be the physical base address of the controller and the 6*4882a593Smuzhiyun length of memory mapped region. 7*4882a593Smuzhiyun- interrupts: Should contain the interrupt for the controller. 8*4882a593Smuzhiyun- dmas: Should be one per channel name listed in the dma-names property, 9*4882a593Smuzhiyun as described in atmel-dma.txt and dma.txt files. 10*4882a593Smuzhiyun- dma-names: Identifier string for each DMA request line in the dmas property. 11*4882a593Smuzhiyun Two dmas have to be defined, "tx" and "rx". 12*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 13*4882a593Smuzhiyun Please refer to clock-bindings.txt. 14*4882a593Smuzhiyun- clock-names: Should be one of each entry matching the clocks phandles list: 15*4882a593Smuzhiyun - "pclk" (peripheral clock) Required. 16*4882a593Smuzhiyun - "gclk" (generated clock) Optional (1). 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- pinctrl-0: Should specify pin control groups used for this controller. 20*4882a593Smuzhiyun- princtrl-names: Should contain only one value - "default". 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun(1) : Only the peripheral clock is required. The generated clock is optional 24*4882a593Smuzhiyun and should be set mostly when Master Mode is required. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun i2s@f001c000 { 29*4882a593Smuzhiyun compatible = "microchip,sam9x60-i2smcc"; 30*4882a593Smuzhiyun reg = <0xf001c000 0x100>; 31*4882a593Smuzhiyun interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 32*4882a593Smuzhiyun dmas = <&dma0 33*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 34*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(36))>, 35*4882a593Smuzhiyun <&dma0 36*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 37*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(37))>; 38*4882a593Smuzhiyun dma-names = "tx", "rx"; 39*4882a593Smuzhiyun clocks = <&i2s_clk>, <&i2s_gclk>; 40*4882a593Smuzhiyun clock-names = "pclk", "gclk"; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2s_default>; 43*4882a593Smuzhiyun }; 44