1*4882a593SmuzhiyunImagination Technologies SPDIF Input Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible : Compatible list, must contain "img,spdif-in" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - #sound-dai-cells : Must be equal to 0 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - reg : Offset and length of the register set for the device 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - dmas: Contains an entry for each entry in dma-names. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - dma-names: Must include the following entry: 14*4882a593Smuzhiyun "rx" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - clocks : Contains an entry for each entry in clock-names 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun - clock-names : Includes the following entries: 19*4882a593Smuzhiyun "sys" The system clock 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional Properties: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - resets: Should contain a phandle to the spdif in reset signal, if any 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - reset-names: Should contain the reset signal name "rst", if a 26*4882a593Smuzhiyun reset phandle is given 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - interrupts : Contains the spdif in interrupt, if present 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunspdif_in: spdif-in@18100e00 { 33*4882a593Smuzhiyun compatible = "img,spdif-in"; 34*4882a593Smuzhiyun reg = <0x18100E00 0x100>; 35*4882a593Smuzhiyun interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 36*4882a593Smuzhiyun dmas = <&mdc 15 0xffffffff 0>; 37*4882a593Smuzhiyun dma-names = "rx"; 38*4882a593Smuzhiyun clocks = <&cr_periph SYS_CLK_SPDIF_IN>; 39*4882a593Smuzhiyun clock-names = "sys"; 40*4882a593Smuzhiyun #sound-dai-cells = <0>; 41*4882a593Smuzhiyun}; 42