1*4882a593SmuzhiyunImagination Technologies I2S Output Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible : Compatible list, must contain "img,i2s-out" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - #sound-dai-cells : Must be equal to 0 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - reg : Offset and length of the register set for the device 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - clocks : Contains an entry for each entry in clock-names 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - clock-names : Must include the following entries: 14*4882a593Smuzhiyun "sys" The system clock 15*4882a593Smuzhiyun "ref" The reference clock 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun - dmas: Contains an entry for each entry in dma-names. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - dma-names: Must include the following entry: 20*4882a593Smuzhiyun "tx" Single DMA channel used by all active I2S channels 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - img,i2s-channels : Number of I2S channels instantiated in the I2S out block 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun - resets: Contains a phandle to the I2S out reset signal 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun - reset-names: Contains the reset signal name "rst" 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunOptional Properties: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun - interrupts : Contains the I2S out interrupts. Depending on 31*4882a593Smuzhiyun the configuration, there may be no interrupts, one interrupt, 32*4882a593Smuzhiyun or an interrupt per I2S channel. For the case where there is 33*4882a593Smuzhiyun one interrupt per channel, the interrupts should be listed 34*4882a593Smuzhiyun in ascending channel order 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyuni2s_out: i2s-out@18100a00 { 39*4882a593Smuzhiyun compatible = "img,i2s-out"; 40*4882a593Smuzhiyun reg = <0x18100A00 0x200>; 41*4882a593Smuzhiyun interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>; 42*4882a593Smuzhiyun dmas = <&mdc 23 0xffffffff 0>; 43*4882a593Smuzhiyun dma-names = "tx"; 44*4882a593Smuzhiyun clocks = <&cr_periph SYS_CLK_I2S_OUT>, 45*4882a593Smuzhiyun <&clk_core CLK_I2S>; 46*4882a593Smuzhiyun clock-names = "sys", "ref"; 47*4882a593Smuzhiyun img,i2s-channels = <6>; 48*4882a593Smuzhiyun resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>; 49*4882a593Smuzhiyun reset-names = "rst"; 50*4882a593Smuzhiyun #sound-dai-cells = <0>; 51*4882a593Smuzhiyun}; 52