xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/fsl-sai.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunFreescale Synchronous Audio Interface (SAI).
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe SAI is based on I2S module that used communicating with audio codecs,
4*4882a593Smuzhiyunwhich provides a synchronous audio interface that supports fullduplex
5*4882a593Smuzhiyunserial interfaces with frame synchronization such as I2S, AC97, TDM, and
6*4882a593Smuzhiyuncodec/DSP interfaces.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunRequired properties:
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun  - compatible		: Compatible list, contains "fsl,vf610-sai",
11*4882a593Smuzhiyun			  "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12*4882a593Smuzhiyun			  "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or
13*4882a593Smuzhiyun			  "fsl,imx8qm-sai".
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun  - reg			: Offset and length of the register set for the device.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun  - clocks		: Must contain an entry for each entry in clock-names.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  - clock-names		: Must include the "bus" for register access and
20*4882a593Smuzhiyun			  "mclk1", "mclk2", "mclk3" for bit clock and frame
21*4882a593Smuzhiyun			  clock providing.
22*4882a593Smuzhiyun  - dmas		: Generic dma devicetree binding as described in
23*4882a593Smuzhiyun			  Documentation/devicetree/bindings/dma/dma.txt.
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  - dma-names		: Two dmas have to be defined, "tx" and "rx".
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  - pinctrl-names	: Must contain a "default" entry.
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  - pinctrl-NNN		: One property must exist for each entry in
30*4882a593Smuzhiyun			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
31*4882a593Smuzhiyun			  for details of the property values.
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  - lsb-first		: Configures whether the LSB or the MSB is transmitted
34*4882a593Smuzhiyun			  first for the fifo data. If this property is absent,
35*4882a593Smuzhiyun			  the MSB is transmitted first as default, or the LSB
36*4882a593Smuzhiyun			  is transmitted first.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
39*4882a593Smuzhiyun			  that SAI will work in the synchronous mode (sync Tx
40*4882a593Smuzhiyun			  with Rx) which means both the transmitter and the
41*4882a593Smuzhiyun			  receiver will send and receive data by following
42*4882a593Smuzhiyun			  receiver's bit clocks and frame sync clocks.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  - fsl,sai-asynchronous: This is a boolean property. If present, indicating
45*4882a593Smuzhiyun			  that SAI will work in the asynchronous mode, which
46*4882a593Smuzhiyun			  means both transmitter and receiver will send and
47*4882a593Smuzhiyun			  receive data by following their own bit clocks and
48*4882a593Smuzhiyun			  frame sync clocks separately.
49*4882a593Smuzhiyun
50*4882a593SmuzhiyunOptional properties:
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun  - big-endian		: Boolean property, required if all the SAI
53*4882a593Smuzhiyun			  registers are big-endian rather than little-endian.
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunOptional properties (for mx6ul):
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun  - fsl,sai-mclk-direction-output: This is a boolean property. If present,
58*4882a593Smuzhiyun			 indicates that SAI will output the SAI MCLK clock.
59*4882a593Smuzhiyun
60*4882a593SmuzhiyunNote:
61*4882a593Smuzhiyun- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
62*4882a593Smuzhiyun  default synchronous mode (sync Rx with Tx) will be used, which means both
63*4882a593Smuzhiyun  transmitter and receiver will send and receive data by following clocks
64*4882a593Smuzhiyun  of transmitter.
65*4882a593Smuzhiyun- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
66*4882a593Smuzhiyun
67*4882a593SmuzhiyunExample:
68*4882a593Smuzhiyunsai2: sai@40031000 {
69*4882a593Smuzhiyun	      compatible = "fsl,vf610-sai";
70*4882a593Smuzhiyun	      reg = <0x40031000 0x1000>;
71*4882a593Smuzhiyun	      pinctrl-names = "default";
72*4882a593Smuzhiyun	      pinctrl-0 = <&pinctrl_sai2_1>;
73*4882a593Smuzhiyun	      clocks = <&clks VF610_CLK_PLATFORM_BUS>,
74*4882a593Smuzhiyun		     <&clks VF610_CLK_SAI2>,
75*4882a593Smuzhiyun		     <&clks 0>, <&clks 0>;
76*4882a593Smuzhiyun	      clock-names = "bus", "mclk1", "mclk2", "mclk3";
77*4882a593Smuzhiyun	      dma-names = "tx", "rx";
78*4882a593Smuzhiyun	      dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
79*4882a593Smuzhiyun		   <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
80*4882a593Smuzhiyun	      big-endian;
81*4882a593Smuzhiyun	      lsb-first;
82*4882a593Smuzhiyun};
83