1*4882a593Smuzhiyunfsl,mqs audio CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs" 5*4882a593Smuzhiyun "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs". 6*4882a593Smuzhiyun - clocks : A list of phandles + clock-specifiers, one for each entry in 7*4882a593Smuzhiyun clock-names 8*4882a593Smuzhiyun - clock-names : "mclk" - must required. 9*4882a593Smuzhiyun "core" - required if compatible is "fsl,imx8qm-mqs", it 10*4882a593Smuzhiyun is for register access. 11*4882a593Smuzhiyun - gpr : A phandle of General Purpose Registers in IOMUX Controller. 12*4882a593Smuzhiyun Required if compatible is "fsl,imx6sx-mqs". 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired if compatible is "fsl,imx8qm-mqs": 15*4882a593Smuzhiyun - power-domains: A phandle of PM domain provider node. 16*4882a593Smuzhiyun - reg: Offset and length of the register set for the device. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunmqs: mqs { 21*4882a593Smuzhiyun compatible = "fsl,imx6sx-mqs"; 22*4882a593Smuzhiyun gpr = <&gpr>; 23*4882a593Smuzhiyun clocks = <&clks IMX6SX_CLK_SAI1>; 24*4882a593Smuzhiyun clock-names = "mclk"; 25*4882a593Smuzhiyun status = "disabled"; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunmqs: mqs@59850000 { 29*4882a593Smuzhiyun compatible = "fsl,imx8qm-mqs"; 30*4882a593Smuzhiyun reg = <0x59850000 0x10000>; 31*4882a593Smuzhiyun clocks = <&clk IMX8QM_AUD_MQS_IPG>, 32*4882a593Smuzhiyun <&clk IMX8QM_AUD_MQS_HMCLK>; 33*4882a593Smuzhiyun clock-names = "core", "mclk"; 34*4882a593Smuzhiyun power-domains = <&pd_mqs0>; 35*4882a593Smuzhiyun status = "disabled"; 36*4882a593Smuzhiyun}; 37