1*4882a593SmuzhiyunNXP MICFIL Digital Audio Interface (MICFIL). 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe MICFIL digital interface provides a 16-bit audio signal from a PDM 4*4882a593Smuzhiyunmicrophone bitstream in a configurable output sampling rate. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun - compatible : Compatible list, contains "fsl,imx8mm-micfil" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun - reg : Offset and length of the register set for the device. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun - interrupts : Contains the micfil interrupts. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - clocks : Must contain an entry for each entry in clock-names. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - clock-names : Must include the "ipg_clk" for register access and 17*4882a593Smuzhiyun "ipg_clk_app" for internal micfil clock. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - dmas : Generic dma devicetree binding as described in 20*4882a593Smuzhiyun Documentation/devicetree/bindings/dma/dma.txt. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyunmicfil: micfil@30080000 { 24*4882a593Smuzhiyun compatible = "fsl,imx8mm-micfil"; 25*4882a593Smuzhiyun reg = <0x0 0x30080000 0x0 0x10000>; 26*4882a593Smuzhiyun interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 27*4882a593Smuzhiyun <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 28*4882a593Smuzhiyun clocks = <&clk IMX8MM_CLK_PDM_IPG>, 29*4882a593Smuzhiyun <&clk IMX8MM_CLK_PDM_ROOT>; 30*4882a593Smuzhiyun clock-names = "ipg_clk", "ipg_clk_app"; 31*4882a593Smuzhiyun dmas = <&sdma2 24 26 0x80000000>; 32*4882a593Smuzhiyun}; 33