1*4882a593SmuzhiyunFreescale Synchronous Serial Interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe SSI is a serial device that communicates with audio codecs. It can 4*4882a593Smuzhiyunbe programmed in AC97, I2S, left-justified, or right-justified modes. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: Compatible list, should contain one of the following 8*4882a593Smuzhiyun compatibles: 9*4882a593Smuzhiyun fsl,mpc8610-ssi 10*4882a593Smuzhiyun fsl,imx51-ssi 11*4882a593Smuzhiyun fsl,imx35-ssi 12*4882a593Smuzhiyun fsl,imx21-ssi 13*4882a593Smuzhiyun- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. 14*4882a593Smuzhiyun- reg: Offset and length of the register set for the device. 15*4882a593Smuzhiyun- interrupts: <a b> where a is the interrupt number and b is a 16*4882a593Smuzhiyun field that represents an encoding of the sense and 17*4882a593Smuzhiyun level information for the interrupt. This should be 18*4882a593Smuzhiyun encoded based on the information in section 2) 19*4882a593Smuzhiyun depending on the type of interrupt controller you 20*4882a593Smuzhiyun have. 21*4882a593Smuzhiyun- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. 22*4882a593Smuzhiyun This number is the maximum allowed value for SFCSR[TFWM0]. 23*4882a593Smuzhiyun - clocks: "ipg" - Required clock for the SSI unit 24*4882a593Smuzhiyun "baud" - Required clock for SSI master mode. Otherwise this 25*4882a593Smuzhiyun clock is not used 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunRequired are also ac97 link bindings if ac97 is used. See 28*4882a593SmuzhiyunDocumentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary 29*4882a593Smuzhiyunbindings. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- codec-handle: Phandle to a 'codec' node that defines an audio 33*4882a593Smuzhiyun codec connected to this SSI. This node is typically 34*4882a593Smuzhiyun a child of an I2C or other control node. 35*4882a593Smuzhiyun- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to 36*4882a593Smuzhiyun filter the codec stream. This is necessary for some boards 37*4882a593Smuzhiyun where an incompatible codec is connected to this SSI, e.g. 38*4882a593Smuzhiyun on pca100 and pcm043. 39*4882a593Smuzhiyun- dmas: Generic dma devicetree binding as described in 40*4882a593Smuzhiyun Documentation/devicetree/bindings/dma/dma.txt. 41*4882a593Smuzhiyun- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq 42*4882a593Smuzhiyun is not defined. 43*4882a593Smuzhiyun- fsl,mode: The operating mode for the AC97 interface only. 44*4882a593Smuzhiyun "ac97-slave" - AC97 mode, SSI is clock slave 45*4882a593Smuzhiyun "ac97-master" - AC97 mode, SSI is clock master 46*4882a593Smuzhiyun- fsl,ssi-asynchronous: 47*4882a593Smuzhiyun If specified, the SSI is to be programmed in asynchronous 48*4882a593Smuzhiyun mode. In this mode, pins SRCK, STCK, SRFS, and STFS must 49*4882a593Smuzhiyun all be connected to valid signals. In synchronous mode, 50*4882a593Smuzhiyun SRCK and SRFS are ignored. Asynchronous mode allows 51*4882a593Smuzhiyun playback and capture to use different sample sizes and 52*4882a593Smuzhiyun sample rates. Some drivers may require that SRCK and STCK 53*4882a593Smuzhiyun be connected together, and SRFS and STFS be connected 54*4882a593Smuzhiyun together. This would still allow different sample sizes, 55*4882a593Smuzhiyun but not different sample rates. 56*4882a593Smuzhiyun- fsl,playback-dma: Phandle to a node for the DMA channel to use for 57*4882a593Smuzhiyun playback of audio. This is typically dictated by SOC 58*4882a593Smuzhiyun design. See the notes below. 59*4882a593Smuzhiyun Only used on Power Architecture. 60*4882a593Smuzhiyun- fsl,capture-dma: Phandle to a node for the DMA channel to use for 61*4882a593Smuzhiyun capture (recording) of audio. This is typically dictated 62*4882a593Smuzhiyun by SOC design. See the notes below. 63*4882a593Smuzhiyun Only used on Power Architecture. 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunChild 'codec' node required properties: 66*4882a593Smuzhiyun- compatible: Compatible list, contains the name of the codec 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunChild 'codec' node optional properties: 69*4882a593Smuzhiyun- clock-frequency: The frequency of the input clock, which typically comes 70*4882a593Smuzhiyun from an on-board dedicated oscillator. 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunNotes on fsl,playback-dma and fsl,capture-dma: 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunOn SOCs that have an SSI, specific DMA channels are hard-wired for playback 75*4882a593Smuzhiyunand capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for 76*4882a593Smuzhiyunplayback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for 77*4882a593Smuzhiyunplayback and DMA channel 3 for capture. The developer can choose which 78*4882a593SmuzhiyunDMA controller to use, but the channels themselves are hard-wired. The 79*4882a593Smuzhiyunpurpose of these two properties is to represent this hardware design. 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunThe device tree nodes for the DMA channels that are referenced by 82*4882a593Smuzhiyun"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with 83*4882a593Smuzhiyun"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. 84*4882a593Smuzhiyun"fsl,mpc8610-dma-channel") can remain. If these nodes are left as 85*4882a593Smuzhiyun"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA 86*4882a593Smuzhiyundrivers (fsldma) will attempt to use them, and it will conflict with the 87*4882a593Smuzhiyunsound drivers. 88