1*4882a593SmuzhiyunFreescale Enhanced Serial Audio Interface (ESAI) Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port 4*4882a593Smuzhiyunfor serial communication with a variety of serial devices, including industry 5*4882a593Smuzhiyunstandard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and 6*4882a593Smuzhiyunother DSPs. It has up to six transmitters and four receivers. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun - compatible : Compatible list, should contain one of the following 11*4882a593Smuzhiyun compatibles: 12*4882a593Smuzhiyun "fsl,imx35-esai", 13*4882a593Smuzhiyun "fsl,vf610-esai", 14*4882a593Smuzhiyun "fsl,imx6ull-esai", 15*4882a593Smuzhiyun "fsl,imx8qm-esai", 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun - reg : Offset and length of the register set for the device. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - interrupts : Contains the spdif interrupt. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun - dmas : Generic dma devicetree binding as described in 22*4882a593Smuzhiyun Documentation/devicetree/bindings/dma/dma.txt. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun - dma-names : Two dmas have to be defined, "tx" and "rx". 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun - clocks : Contains an entry for each entry in clock-names. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - clock-names : Includes the following entries: 29*4882a593Smuzhiyun "core" The core clock used to access registers 30*4882a593Smuzhiyun "extal" The esai baud clock for esai controller used to 31*4882a593Smuzhiyun derive HCK, SCK and FS. 32*4882a593Smuzhiyun "fsys" The system clock derived from ahb clock used to 33*4882a593Smuzhiyun derive HCK, SCK and FS. 34*4882a593Smuzhiyun "spba" The spba clock is required when ESAI is placed as a 35*4882a593Smuzhiyun bus slave of the Shared Peripheral Bus and when two 36*4882a593Smuzhiyun or more bus masters (CPU, DMA or DSP) try to access 37*4882a593Smuzhiyun it. This property is optional depending on the SoC 38*4882a593Smuzhiyun design. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun - fsl,fifo-depth : The number of elements in the transmit and receive 41*4882a593Smuzhiyun FIFOs. This number is the maximum allowed value for 42*4882a593Smuzhiyun TFCR[TFWM] or RFCR[RFWM]. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun - fsl,esai-synchronous: This is a boolean property. If present, indicating 45*4882a593Smuzhiyun that ESAI would work in the synchronous mode, which 46*4882a593Smuzhiyun means all the settings for Receiving would be 47*4882a593Smuzhiyun duplicated from Transmition related registers. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunOptional properties: 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun - big-endian : If this property is absent, the native endian mode 52*4882a593Smuzhiyun will be in use as default, or the big endian mode 53*4882a593Smuzhiyun will be in use for all the device registers. 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunesai: esai@2024000 { 58*4882a593Smuzhiyun compatible = "fsl,imx35-esai"; 59*4882a593Smuzhiyun reg = <0x02024000 0x4000>; 60*4882a593Smuzhiyun interrupts = <0 51 0x04>; 61*4882a593Smuzhiyun clocks = <&clks 208>, <&clks 118>, <&clks 208>; 62*4882a593Smuzhiyun clock-names = "core", "extal", "fsys"; 63*4882a593Smuzhiyun dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 64*4882a593Smuzhiyun dma-names = "rx", "tx"; 65*4882a593Smuzhiyun fsl,fifo-depth = <128>; 66*4882a593Smuzhiyun fsl,esai-synchronous; 67*4882a593Smuzhiyun big-endian; 68*4882a593Smuzhiyun}; 69