1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/sound/fsl,easrc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP Asynchronous Sample Rate Converter (ASRC) Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Shengjiu Wang <shengjiu.wang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun $nodename: 14*4882a593Smuzhiyun pattern: "^easrc@.*" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: fsl,imx8mn-easrc 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: Peripheral clock 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clock-names: 30*4882a593Smuzhiyun items: 31*4882a593Smuzhiyun - const: mem 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun dmas: 34*4882a593Smuzhiyun maxItems: 8 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun dma-names: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: ctx0_rx 39*4882a593Smuzhiyun - const: ctx0_tx 40*4882a593Smuzhiyun - const: ctx1_rx 41*4882a593Smuzhiyun - const: ctx1_tx 42*4882a593Smuzhiyun - const: ctx2_rx 43*4882a593Smuzhiyun - const: ctx2_tx 44*4882a593Smuzhiyun - const: ctx3_rx 45*4882a593Smuzhiyun - const: ctx3_tx 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun firmware-name: 48*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/string 49*4882a593Smuzhiyun const: imx/easrc/easrc-imx8mn.bin 50*4882a593Smuzhiyun description: The coefficient table for the filters 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun fsl,asrc-rate: 53*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 54*4882a593Smuzhiyun minimum: 8000 55*4882a593Smuzhiyun maximum: 192000 56*4882a593Smuzhiyun description: Defines a mutual sample rate used by DPCM Back Ends 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun fsl,asrc-format: 59*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 60*4882a593Smuzhiyun enum: [2, 6, 10, 32, 36] 61*4882a593Smuzhiyun default: 2 62*4882a593Smuzhiyun description: 63*4882a593Smuzhiyun Defines a mutual sample format used by DPCM Back Ends 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunrequired: 66*4882a593Smuzhiyun - compatible 67*4882a593Smuzhiyun - reg 68*4882a593Smuzhiyun - interrupts 69*4882a593Smuzhiyun - clocks 70*4882a593Smuzhiyun - clock-names 71*4882a593Smuzhiyun - dmas 72*4882a593Smuzhiyun - dma-names 73*4882a593Smuzhiyun - firmware-name 74*4882a593Smuzhiyun - fsl,asrc-rate 75*4882a593Smuzhiyun - fsl,asrc-format 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunadditionalProperties: false 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunexamples: 80*4882a593Smuzhiyun - | 81*4882a593Smuzhiyun #include <dt-bindings/clock/imx8mn-clock.h> 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun easrc: easrc@300c0000 { 84*4882a593Smuzhiyun compatible = "fsl,imx8mn-easrc"; 85*4882a593Smuzhiyun reg = <0x300c0000 0x10000>; 86*4882a593Smuzhiyun interrupts = <0x0 122 0x4>; 87*4882a593Smuzhiyun clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 88*4882a593Smuzhiyun clock-names = "mem"; 89*4882a593Smuzhiyun dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 90*4882a593Smuzhiyun <&sdma2 18 23 0> , <&sdma2 19 23 0>, 91*4882a593Smuzhiyun <&sdma2 20 23 0> , <&sdma2 21 23 0>, 92*4882a593Smuzhiyun <&sdma2 22 23 0> , <&sdma2 23 23 0>; 93*4882a593Smuzhiyun dma-names = "ctx0_rx", "ctx0_tx", 94*4882a593Smuzhiyun "ctx1_rx", "ctx1_tx", 95*4882a593Smuzhiyun "ctx2_rx", "ctx2_tx", 96*4882a593Smuzhiyun "ctx3_rx", "ctx3_tx"; 97*4882a593Smuzhiyun firmware-name = "imx/easrc/easrc-imx8mn.bin"; 98*4882a593Smuzhiyun fsl,asrc-rate = <8000>; 99*4882a593Smuzhiyun fsl,asrc-format = <2>; 100*4882a593Smuzhiyun }; 101