1*4882a593SmuzhiyunEverest ES8311 audio CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible: "everest,es8311" 6*4882a593Smuzhiyun - reg: the I2C address of the device for I2C 7*4882a593Smuzhiyun - spk-ctl-gpios: control spk enable/disable 8*4882a593SmuzhiyunOptional properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- clocks: The phandle of the master clock to the CODEC 11*4882a593Smuzhiyun- clock-names: Should be "mclk" 12*4882a593Smuzhiyun- adc-pga-gain: The PGA Gain of ADC, the value range is: 0(0dB) ~ 10(30dB), 13*4882a593Smuzhiyun the step is 3dB. 14*4882a593Smuzhiyun- adc-volume: The volume of ADC, range is: 0x00(-95dB) ~ 0xff(+32dB), 0dB is 0xbf. 15*4882a593Smuzhiyun- dac-volume: The volume of DAC, range is: 0x00(-95dB) ~ 0xff(+32dB), 0dB is 0xbf. 16*4882a593Smuzhiyun- aec-mode: The string of description AEC path between ADC and DAC, It should be: 17*4882a593Smuzhiyun "adc left, adc right", 18*4882a593Smuzhiyun "adc left, null right", 19*4882a593Smuzhiyun "null left, adc right", 20*4882a593Smuzhiyun "null left, null right", 21*4882a593Smuzhiyun "dac left, adc right", 22*4882a593Smuzhiyun "adc left, dac right", 23*4882a593Smuzhiyun "dac left, dac right" 24*4882a593Smuzhiyun And aec-mode is "adc left, adc right" by default, if the property 25*4882a593Smuzhiyun is not specified. 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunes8311: es8311@18 { 29*4882a593Smuzhiyun compatible = "everest,es8311"; 30*4882a593Smuzhiyun reg = <0x18>; 31*4882a593Smuzhiyun clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 32*4882a593Smuzhiyun clock-names = "mclk"; 33*4882a593Smuzhiyun adc-pga-gain = <0>; /* 0dB */ 34*4882a593Smuzhiyun adc-volume = <0xbf>; /* 0dB */ 35*4882a593Smuzhiyun dac-volume = <0xbf>; /* 0dB */ 36*4882a593Smuzhiyun aec-mode = "dac left, adc right"; 37*4882a593Smuzhiyun spk-ctl-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 38*4882a593Smuzhiyun}; 39