1*4882a593SmuzhiyunDesignWare I2S controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Must be "snps,designware-i2s" 5*4882a593Smuzhiyun - reg : Must contain the I2S core's registers location and length 6*4882a593Smuzhiyun - clocks : Pairs of phandle and specifier referencing the controller's 7*4882a593Smuzhiyun clocks. The controller expects one clock: the clock used as the sampling 8*4882a593Smuzhiyun rate reference clock sample. 9*4882a593Smuzhiyun - clock-names : "i2sclk" for the sample rate reference clock. 10*4882a593Smuzhiyun - dmas: Pairs of phandle and specifier for the DMA channels that are used by 11*4882a593Smuzhiyun the core. The core expects one or two dma channels: one for transmit and 12*4882a593Smuzhiyun one for receive. 13*4882a593Smuzhiyun - dma-names : "tx" for the transmit channel, "rx" for the receive channel. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun - interrupts: The interrupt line number for the I2S controller. Add this 17*4882a593Smuzhiyun parameter if the I2S controller that you are using does not support DMA. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunFor more details on the 'dma', 'dma-names', 'clock' and 'clock-names' 20*4882a593Smuzhiyunproperties please check: 21*4882a593Smuzhiyun * resource-names.txt 22*4882a593Smuzhiyun * clock/clock-bindings.txt 23*4882a593Smuzhiyun * dma/dma.txt 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun soc_i2s: i2s@7ff90000 { 28*4882a593Smuzhiyun compatible = "snps,designware-i2s"; 29*4882a593Smuzhiyun reg = <0x0 0x7ff90000 0x0 0x1000>; 30*4882a593Smuzhiyun clocks = <&scpi_i2sclk 0>; 31*4882a593Smuzhiyun clock-names = "i2sclk"; 32*4882a593Smuzhiyun #sound-dai-cells = <0>; 33*4882a593Smuzhiyun dmas = <&dma0 5>; 34*4882a593Smuzhiyun dma-names = "tx"; 35*4882a593Smuzhiyun }; 36