1*4882a593SmuzhiyunCS42448/CS42888 audio CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - reg : the I2C address of the device for I2C 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - clocks : a list of phandles + clock-specifiers, one for each entry in 10*4882a593Smuzhiyun clock-names 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun - clock-names : must contain "mclk" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device, 15*4882a593Smuzhiyun as covered in Documentation/devicetree/bindings/regulator/regulator.txt 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - reset-gpios : a GPIO spec to define which pin is connected to the chip's 20*4882a593Smuzhiyun !RESET pin 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyuncs42888: codec@48 { 25*4882a593Smuzhiyun compatible = "cirrus,cs42888"; 26*4882a593Smuzhiyun reg = <0x48>; 27*4882a593Smuzhiyun clocks = <&codec_mclk 0>; 28*4882a593Smuzhiyun clock-names = "mclk"; 29*4882a593Smuzhiyun VA-supply = <®_audio>; 30*4882a593Smuzhiyun VD-supply = <®_audio>; 31*4882a593Smuzhiyun VLS-supply = <®_audio>; 32*4882a593Smuzhiyun VLC-supply = <®_audio>; 33*4882a593Smuzhiyun reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun}; 35