xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/cs35l33.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunCS35L33 Speaker Amplifier
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun  - compatible : "cirrus,cs35l33"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun  - reg : the I2C address of the device for I2C
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun  - VA-supply, VP-supply : power supplies for the device,
10*4882a593Smuzhiyun    as covered in
11*4882a593Smuzhiyun    Documentation/devicetree/bindings/regulator/regulator.txt.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunOptional properties:
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun  - reset-gpios : gpio used to reset the amplifier
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun -  interrupts : IRQ line info CS35L33.
18*4882a593Smuzhiyun    (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
19*4882a593Smuzhiyun    for further information relating to interrupt properties)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
22*4882a593Smuzhiyun    0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23*4882a593Smuzhiyun    a value of 1 and will increase at a step size of 100mV until a maximum of
24*4882a593Smuzhiyun    8000mV.
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  - cirrus,ramp-rate : On power up, it affects the time from when the power
27*4882a593Smuzhiyun    up sequence begins to the time the audio reaches a full-scale output.
28*4882a593Smuzhiyun    On power down, it affects the time from when the power-down sequence
29*4882a593Smuzhiyun    begins to when the amplifier disables the PWM outputs. If this property
30*4882a593Smuzhiyun    is not set then soft ramping will be disabled and ramp time would be
31*4882a593Smuzhiyun    20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
32*4882a593Smuzhiyun    60ms,100ms,175ms respectively for 48KHz sample rate.
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  - cirrus,boost-ipk : The maximum current allowed for the boost converter.
35*4882a593Smuzhiyun    The range starts at 1850000uA and goes to a maximum of 3600000uA
36*4882a593Smuzhiyun    with a step size of 15625uA. The default is 2500000uA.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
39*4882a593Smuzhiyun    ADC data word. This property can be set as a value of 0 for bits 15 down
40*4882a593Smuzhiyun    to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun
43*4882a593SmuzhiyunOptional H/G Algorithm sub-node:
44*4882a593Smuzhiyun
45*4882a593SmuzhiyunThe cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
46*4882a593Smuzhiyunthe internal H/G Algorithm.
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun  - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
49*4882a593Smuzhiyun    controls the amplifier supplies.
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunOptional properties for the "cirrus,hg-algo" sub-node:
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
54*4882a593Smuzhiyun    LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55*4882a593Smuzhiyun    depths will be 1, 4, 8, 16 LRCLK cycles.  The default is 16 LRCLK cycles.
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun    cirrus,release-rate : The number of consecutive LRCLK periods before
58*4882a593Smuzhiyun    allowing release condition tracking updates. The number of LRCLK periods
59*4882a593Smuzhiyun    start at 3 to a maximum of 255.
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun  - cirrus,ldo-thld : Configures the signal threshold at which the PWM output
62*4882a593Smuzhiyun    stage enters LDO operation. Starts as a default value of 50mV for a value
63*4882a593Smuzhiyun    of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
64*4882a593Smuzhiyun    0xF).
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun  - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
67*4882a593Smuzhiyun    algorithm uses the max detection path.  If not present, the LDO
68*4882a593Smuzhiyun    detection path is used.
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun  - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
71*4882a593Smuzhiyun    algorithm switches to the LDO voltage.  This property can be set to values
72*4882a593Smuzhiyun    from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
73*4882a593Smuzhiyun    The default is 100ms.
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun  - cirrus,vp-hg-auto : This is a boolean property.  When set, class H/G VPhg
76*4882a593Smuzhiyun    automatic updating is enabled.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun  - cirrus,vp-hg :  Class H/G algorithm VPhg.  Controls the H/G algorithm's
79*4882a593Smuzhiyun    reference to the VP voltage for when to start generating a boosted VBST.
80*4882a593Smuzhiyun    The reference voltage starts at 3000mV with a value of 0x3 and is increased
81*4882a593Smuzhiyun    by 100mV per step to a maximum of 5500mV.
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun  - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
84*4882a593Smuzhiyun    allowed to increase to a higher voltage when using VPhg automatic
85*4882a593Smuzhiyun    tracking. This property can be set to values from 0 to 3 with rates of 128
86*4882a593Smuzhiyun    periods, 2048 periods, 32768 periods, and 524288 periods.
87*4882a593Smuzhiyun    The default is 32768 periods.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun  - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
90*4882a593Smuzhiyun    using VPMON. This property can be set to values from 0 to 6 starting at
91*4882a593Smuzhiyun    1800mV with a step size of 50mV up to a maximum value of 1750mV.
92*4882a593Smuzhiyun    Default is 1800mV.
93*4882a593Smuzhiyun
94*4882a593SmuzhiyunExample:
95*4882a593Smuzhiyun
96*4882a593Smuzhiyuncs35l33: cs35l33@40 {
97*4882a593Smuzhiyun	compatible = "cirrus,cs35l33";
98*4882a593Smuzhiyun	reg = <0x40>;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	VA-supply = <&ldo5_reg>;
101*4882a593Smuzhiyun	VP-supply = <&ldo5_reg>;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	interrupt-parent = <&gpio8>;
104*4882a593Smuzhiyun	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	reset-gpios = <&cs47l91 34 0>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	cirrus,ramp-rate = <0x0>;
109*4882a593Smuzhiyun	cirrus,boost-ctl = <0x30>;  /* VBST = 8000mV */
110*4882a593Smuzhiyun	cirrus,boost-ipk = <0xE0>; /* 3600mA */
111*4882a593Smuzhiyun	cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	cirrus,hg-algo {
114*4882a593Smuzhiyun		cirrus,mem-depth = <0x3>;
115*4882a593Smuzhiyun		cirrus,release-rate = <0x3>;
116*4882a593Smuzhiyun		cirrus,ldo-thld = <0x1>;
117*4882a593Smuzhiyun		cirrus,ldo-path-disable = <0x0>;
118*4882a593Smuzhiyun		cirrus,ldo-entry-delay=<0x4>;
119*4882a593Smuzhiyun		cirrus,vp-hg-auto;
120*4882a593Smuzhiyun		cirrus,vp-hg=<0xF>;
121*4882a593Smuzhiyun		cirrus,vp-hg-rate=<0x2>;
122*4882a593Smuzhiyun		cirrus,vp-hg-va=<0x0>;
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun};
125