1*4882a593SmuzhiyunBindings for I2S controller built into xtfpga Xtensa bitstreams. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: shall be "cdns,xtfpga-i2s". 5*4882a593Smuzhiyun- reg: memory region (address and length) with device registers. 6*4882a593Smuzhiyun- interrupts: interrupt for the device. 7*4882a593Smuzhiyun- clocks: phandle to the clk used as master clock. I2S bus clock 8*4882a593Smuzhiyun is derived from it. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunExamples: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun i2s0: xtfpga-i2s@d080000 { 13*4882a593Smuzhiyun #sound-dai-cells = <0>; 14*4882a593Smuzhiyun compatible = "cdns,xtfpga-i2s"; 15*4882a593Smuzhiyun reg = <0x0d080000 0x40>; 16*4882a593Smuzhiyun interrupts = <2 1>; 17*4882a593Smuzhiyun clocks = <&cdce706 4>; 18*4882a593Smuzhiyun }; 19