1*4882a593SmuzhiyunBROADCOM Cygnus Audio I2S/TDM/SPDIF controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : "brcm,cygnus-audio" 5*4882a593Smuzhiyun - #address-cells: 32bit valued, 1 cell. 6*4882a593Smuzhiyun - #size-cells: 32bit valued, 0 cell. 7*4882a593Smuzhiyun - reg : Should contain audio registers location and length 8*4882a593Smuzhiyun - reg-names: names of the registers listed in "reg" property 9*4882a593Smuzhiyun Valid names are "aud" and "i2s_in". "aud" contains a 10*4882a593Smuzhiyun set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains 11*4882a593Smuzhiyun a set of I2S_IN registers. 12*4882a593Smuzhiyun - clocks: PLL and leaf clocks used by audio ports 13*4882a593Smuzhiyun - assigned-clocks: PLL and leaf clocks 14*4882a593Smuzhiyun - assigned-clock-parents: parent clocks of the assigned clocks 15*4882a593Smuzhiyun (usually the PLL) 16*4882a593Smuzhiyun - assigned-clock-rates: List of clock frequencies of the 17*4882a593Smuzhiyun assigned clocks 18*4882a593Smuzhiyun - clock-names: names of 3 leaf clocks used by audio ports 19*4882a593Smuzhiyun Valid names are "ch0_audio", "ch1_audio", "ch2_audio" 20*4882a593Smuzhiyun - interrupts: audio DMA interrupt number 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunSSP Subnode properties: 23*4882a593Smuzhiyun- reg: The index of ssp port interface to use 24*4882a593Smuzhiyun Valid value are 0, 1, 2, or 3 (for spdif) 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun cygnus_audio: audio@180ae000 { 28*4882a593Smuzhiyun compatible = "brcm,cygnus-audio"; 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>; 32*4882a593Smuzhiyun reg-names = "aud", "i2s_in"; 33*4882a593Smuzhiyun clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, 34*4882a593Smuzhiyun <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, 35*4882a593Smuzhiyun <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; 36*4882a593Smuzhiyun assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>, 37*4882a593Smuzhiyun <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, 38*4882a593Smuzhiyun <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, 39*4882a593Smuzhiyun <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; 40*4882a593Smuzhiyun assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>; 41*4882a593Smuzhiyun assigned-clock-rates = <1769470191>, 42*4882a593Smuzhiyun <0>, 43*4882a593Smuzhiyun <0>, 44*4882a593Smuzhiyun <0>; 45*4882a593Smuzhiyun clock-names = "ch0_audio", "ch1_audio", "ch2_audio"; 46*4882a593Smuzhiyun interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ssp0: ssp_port@0 { 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ssp1: ssp_port@1 { 53*4882a593Smuzhiyun reg = <1>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ssp2: ssp_port@2 { 57*4882a593Smuzhiyun reg = <2>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun spdif: spdif_port@3 { 61*4882a593Smuzhiyun reg = <3>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64