1*4882a593Smuzhiyun* Atmel I2S controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "atmel,sama5d2-i2s". 5*4882a593Smuzhiyun- reg: Should be the physical base address of the controller and the 6*4882a593Smuzhiyun length of memory mapped region. 7*4882a593Smuzhiyun- interrupts: Should contain the interrupt for the controller. 8*4882a593Smuzhiyun- dmas: Should be one per channel name listed in the dma-names property, 9*4882a593Smuzhiyun as described in atmel-dma.txt and dma.txt files. 10*4882a593Smuzhiyun- dma-names: Two dmas have to be defined, "tx" and "rx". 11*4882a593Smuzhiyun This IP also supports one shared channel for both rx and tx; 12*4882a593Smuzhiyun if this mode is used, one "rx-tx" name must be used. 13*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 14*4882a593Smuzhiyun Please refer to clock-bindings.txt. 15*4882a593Smuzhiyun- clock-names: Should be one of each entry matching the clocks phandles list: 16*4882a593Smuzhiyun - "pclk" (peripheral clock) Required. 17*4882a593Smuzhiyun - "gclk" (generated clock) Optional (1). 18*4882a593Smuzhiyun - "muxclk" (I2S mux clock) Optional (1). 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- pinctrl-0: Should specify pin control groups used for this controller. 22*4882a593Smuzhiyun- princtrl-names: Should contain only one value - "default". 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun(1) : Only the peripheral clock is required. The generated clock and the I2S 26*4882a593Smuzhiyun mux clock are optional and should only be set together, when Master Mode 27*4882a593Smuzhiyun is required. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun i2s@f8050000 { 32*4882a593Smuzhiyun compatible = "atmel,sama5d2-i2s"; 33*4882a593Smuzhiyun reg = <0xf8050000 0x300>; 34*4882a593Smuzhiyun interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 35*4882a593Smuzhiyun dmas = <&dma0 36*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 37*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(31))>, 38*4882a593Smuzhiyun <&dma0 39*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 40*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(32))>; 41*4882a593Smuzhiyun dma-names = "tx", "rx"; 42*4882a593Smuzhiyun clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>; 43*4882a593Smuzhiyun clock-names = "pclk", "gclk", "muxclk"; 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2s0_default>; 46*4882a593Smuzhiyun }; 47