1*4882a593Smuzhiyun* Atmel ClassD driver under ALSA SoC architecture 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible 5*4882a593Smuzhiyun Should be "atmel,sama5d2-classd". 6*4882a593Smuzhiyun- reg 7*4882a593Smuzhiyun Should contain ClassD registers location and length. 8*4882a593Smuzhiyun- interrupts 9*4882a593Smuzhiyun Should contain the IRQ line for the ClassD. 10*4882a593Smuzhiyun- dmas 11*4882a593Smuzhiyun One DMA specifiers as described in atmel-dma.txt and dma.txt files. 12*4882a593Smuzhiyun- dma-names 13*4882a593Smuzhiyun Must be "tx". 14*4882a593Smuzhiyun- clock-names 15*4882a593Smuzhiyun Tuple listing input clock names. 16*4882a593Smuzhiyun Required elements: "pclk" and "gclk". 17*4882a593Smuzhiyun- clocks 18*4882a593Smuzhiyun Please refer to clock-bindings.txt. 19*4882a593Smuzhiyun- assigned-clocks 20*4882a593Smuzhiyun Should be <&classd_gclk>. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- pinctrl-names, pinctrl-0 24*4882a593Smuzhiyun Please refer to pinctrl-bindings.txt. 25*4882a593Smuzhiyun- atmel,model 26*4882a593Smuzhiyun The user-visible name of this sound complex. 27*4882a593Smuzhiyun The default value is "CLASSD". 28*4882a593Smuzhiyun- atmel,pwm-type 29*4882a593Smuzhiyun PWM modulation type, "single" or "diff". 30*4882a593Smuzhiyun The default value is "single". 31*4882a593Smuzhiyun- atmel,non-overlap-time 32*4882a593Smuzhiyun Set non-overlapping time, the unit is nanosecond(ns). 33*4882a593Smuzhiyun There are four values, 34*4882a593Smuzhiyun <5>, <10>, <15>, <20>, the default value is <10>. 35*4882a593Smuzhiyun Non-overlapping will be disabled if not specified. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample: 38*4882a593Smuzhiyunclassd: classd@fc048000 { 39*4882a593Smuzhiyun compatible = "atmel,sama5d2-classd"; 40*4882a593Smuzhiyun reg = <0xfc048000 0x100>; 41*4882a593Smuzhiyun interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 42*4882a593Smuzhiyun dmas = <&dma0 43*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 44*4882a593Smuzhiyun | AT91_XDMAC_DT_PERID(47))>; 45*4882a593Smuzhiyun dma-names = "tx"; 46*4882a593Smuzhiyun clocks = <&classd_clk>, <&classd_gclk>; 47*4882a593Smuzhiyun clock-names = "pclk", "gclk"; 48*4882a593Smuzhiyun assigned-clocks = <&classd_gclk>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun pinctrl-names = "default"; 51*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_classd_default>; 52*4882a593Smuzhiyun atmel,model = "classd @ SAMA5D2-Xplained"; 53*4882a593Smuzhiyun atmel,pwm-type = "diff"; 54*4882a593Smuzhiyun atmel,non-overlap-time = <10>; 55*4882a593Smuzhiyun}; 56