1*4882a593Smuzhiyun* Amlogic Audio TDM formatters 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 'amlogic,axg-tdmin' or 5*4882a593Smuzhiyun 'amlogic,axg-tdmout' or 6*4882a593Smuzhiyun 'amlogic,g12a-tdmin' or 7*4882a593Smuzhiyun 'amlogic,g12a-tdmout' or 8*4882a593Smuzhiyun 'amlogic,sm1-tdmin' or 9*4882a593Smuzhiyun 'amlogic,sm1-tdmout 10*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory 11*4882a593Smuzhiyun mapped region. 12*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 13*4882a593Smuzhiyun- clock-names: should contain the following: 14*4882a593Smuzhiyun * "pclk" : peripheral clock. 15*4882a593Smuzhiyun * "sclk" : bit clock. 16*4882a593Smuzhiyun * "sclk_sel" : bit clock input multiplexer. 17*4882a593Smuzhiyun * "lrclk" : sample clock 18*4882a593Smuzhiyun * "lrclk_sel": sample clock input multiplexer 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional property: 21*4882a593Smuzhiyun- resets: phandle to the dedicated reset line of the tdm formatter. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample of TDMOUT_A on the S905X2 SoC: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyuntdmout_a: audio-controller@500 { 26*4882a593Smuzhiyun compatible = "amlogic,axg-tdmout"; 27*4882a593Smuzhiyun reg = <0x0 0x500 0x0 0x40>; 28*4882a593Smuzhiyun resets = <&clkc_audio AUD_RESET_TDMOUT_A>; 29*4882a593Smuzhiyun clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 30*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 31*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 32*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 33*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 34*4882a593Smuzhiyun clock-names = "pclk", "sclk", "sclk_sel", 35*4882a593Smuzhiyun "lrclk", "lrclk_sel"; 36*4882a593Smuzhiyun}; 37