1*4882a593Smuzhiyun* Amlogic Audio SPDIF Input 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 'amlogic,axg-spdifin' or 5*4882a593Smuzhiyun 'amlogic,g12a-spdifin' or 6*4882a593Smuzhiyun 'amlogic,sm1-spdifin' 7*4882a593Smuzhiyun- interrupts: interrupt specifier for the spdif input. 8*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 9*4882a593Smuzhiyun- clock-names: should contain the following: 10*4882a593Smuzhiyun * "pclk" : peripheral clock. 11*4882a593Smuzhiyun * "refclk" : spdif input reference clock 12*4882a593Smuzhiyun- #sound-dai-cells: must be 0. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunOptional property: 15*4882a593Smuzhiyun- resets: phandle to the dedicated reset line of the spdif input. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample on the A113 SoC: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunspdifin: audio-controller@400 { 20*4882a593Smuzhiyun compatible = "amlogic,axg-spdifin"; 21*4882a593Smuzhiyun reg = <0x0 0x400 0x0 0x30>; 22*4882a593Smuzhiyun #sound-dai-cells = <0>; 23*4882a593Smuzhiyun interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 24*4882a593Smuzhiyun clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 25*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 26*4882a593Smuzhiyun clock-names = "pclk", "refclk"; 27*4882a593Smuzhiyun}; 28