1*4882a593Smuzhiyun* Amlogic Audio PDM input 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 'amlogic,axg-pdm' or 5*4882a593Smuzhiyun 'amlogic,g12a-pdm' or 6*4882a593Smuzhiyun 'amlogic,sm1-pdm' 7*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory 8*4882a593Smuzhiyun mapped region. 9*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 10*4882a593Smuzhiyun- clock-names: should contain the following: 11*4882a593Smuzhiyun * "pclk" : peripheral clock. 12*4882a593Smuzhiyun * "dclk" : pdm digital clock 13*4882a593Smuzhiyun * "sysclk" : dsp system clock 14*4882a593Smuzhiyun- #sound-dai-cells: must be 0. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional property: 17*4882a593Smuzhiyun- resets: phandle to the dedicated reset line of the pdm input. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample of PDM on the A113 SoC: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunpdm: audio-controller@ff632000 { 22*4882a593Smuzhiyun compatible = "amlogic,axg-pdm"; 23*4882a593Smuzhiyun reg = <0x0 0xff632000 0x0 0x34>; 24*4882a593Smuzhiyun #sound-dai-cells = <0>; 25*4882a593Smuzhiyun clocks = <&clkc_audio AUD_CLKID_PDM>, 26*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_PDM_DCLK>, 27*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 28*4882a593Smuzhiyun clock-names = "pclk", "dclk", "sysclk"; 29*4882a593Smuzhiyun}; 30