1*4882a593Smuzhiyun* Amlogic Audio FIFO controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 'amlogic,axg-toddr' or 5*4882a593Smuzhiyun 'amlogic,axg-toddr' or 6*4882a593Smuzhiyun 'amlogic,g12a-frddr' or 7*4882a593Smuzhiyun 'amlogic,g12a-toddr' or 8*4882a593Smuzhiyun 'amlogic,sm1-frddr' or 9*4882a593Smuzhiyun 'amlogic,sm1-toddr' 10*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory 11*4882a593Smuzhiyun mapped region. 12*4882a593Smuzhiyun- interrupts: interrupt specifier for the fifo. 13*4882a593Smuzhiyun- clocks: phandle to the fifo peripheral clock provided by the audio 14*4882a593Smuzhiyun clock controller. 15*4882a593Smuzhiyun- resets: list of reset phandle, one for each entry reset-names. 16*4882a593Smuzhiyun- reset-names: should contain the following: 17*4882a593Smuzhiyun * "arb" : memory ARB line (required) 18*4882a593Smuzhiyun * "rst" : dedicated device reset line (optional) 19*4882a593Smuzhiyun- #sound-dai-cells: must be 0. 20*4882a593Smuzhiyun- amlogic,fifo-depth: The size of the controller's fifo in bytes. This 21*4882a593Smuzhiyun is useful for determining certain configuration such 22*4882a593Smuzhiyun as the flush threshold of the fifo 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample of FRDDR A on the A113 SoC: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunfrddr_a: audio-controller@1c0 { 27*4882a593Smuzhiyun compatible = "amlogic,axg-frddr"; 28*4882a593Smuzhiyun reg = <0x0 0x1c0 0x0 0x1c>; 29*4882a593Smuzhiyun #sound-dai-cells = <0>; 30*4882a593Smuzhiyun interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 31*4882a593Smuzhiyun clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 32*4882a593Smuzhiyun resets = <&arb AXG_ARB_FRDDR_A>; 33*4882a593Smuzhiyun fifo-depth = <512>; 34*4882a593Smuzhiyun}; 35