1*4882a593Smuzhiyun* Amlogic Audio SPDIF Output 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 'amlogic,axg-spdifout' or 5*4882a593Smuzhiyun 'amlogic,g12a-spdifout' or 6*4882a593Smuzhiyun 'amlogic,sm1-spdifout' 7*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 8*4882a593Smuzhiyun- clock-names: should contain the following: 9*4882a593Smuzhiyun * "pclk" : peripheral clock. 10*4882a593Smuzhiyun * "mclk" : master clock 11*4882a593Smuzhiyun- #sound-dai-cells: must be 0. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional property: 14*4882a593Smuzhiyun- resets: phandle to the dedicated reset line of the spdif output. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample on the A113 SoC: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunspdifout: audio-controller@480 { 19*4882a593Smuzhiyun compatible = "amlogic,axg-spdifout"; 20*4882a593Smuzhiyun reg = <0x0 0x480 0x0 0x50>; 21*4882a593Smuzhiyun #sound-dai-cells = <0>; 22*4882a593Smuzhiyun clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 23*4882a593Smuzhiyun <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 24*4882a593Smuzhiyun clock-names = "pclk", "mclk"; 25*4882a593Smuzhiyun}; 26