1*4882a593SmuzhiyunAnalog Devices ADAU1701 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible: Should contain "adi,adau1701" 6*4882a593Smuzhiyun - reg: The i2c address. Value depends on the state of ADDR0 7*4882a593Smuzhiyun and ADDR1, as wired in hardware. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reset-gpio: A GPIO spec to define which pin is connected to the 12*4882a593Smuzhiyun chip's !RESET pin. If specified, the driver will 13*4882a593Smuzhiyun assert a hardware reset at probe time. 14*4882a593Smuzhiyun - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs 15*4882a593Smuzhiyun the ADAU's PLL config pins are connected to. 16*4882a593Smuzhiyun The state of the pins are set according to the 17*4882a593Smuzhiyun configured clock divider on ASoC side before the 18*4882a593Smuzhiyun firmware is loaded. 19*4882a593Smuzhiyun - adi,pin-config: An array of 12 numerical values selecting one of the 20*4882a593Smuzhiyun pin configurations as described in the datasheet, 21*4882a593Smuzhiyun table 53. Note that the value of this property has 22*4882a593Smuzhiyun to be prefixed with '/bits/ 8'. 23*4882a593Smuzhiyun - avdd-supply: Power supply for AVDD, providing 3.3V 24*4882a593Smuzhiyun - dvdd-supply: Power supply for DVDD, providing 3.3V 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExamples: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun i2c_bus { 29*4882a593Smuzhiyun adau1701@34 { 30*4882a593Smuzhiyun compatible = "adi,adau1701"; 31*4882a593Smuzhiyun reg = <0x34>; 32*4882a593Smuzhiyun reset-gpio = <&gpio 23 0>; 33*4882a593Smuzhiyun avdd-supply = <&vdd_3v3_reg>; 34*4882a593Smuzhiyun dvdd-supply = <&vdd_3v3_reg>; 35*4882a593Smuzhiyun adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; 36*4882a593Smuzhiyun adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 37*4882a593Smuzhiyun 0x4 0x4 0x4 0x4 0x4 0x4>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40