1*4882a593SmuzhiyunADI AXI-SPDIF controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Must be "adi,axi-spdif-tx-1.00.a" 5*4882a593Smuzhiyun - reg : Must contain SPDIF core's registers location and length 6*4882a593Smuzhiyun - clocks : Pairs of phandle and specifier referencing the controller's clocks. 7*4882a593Smuzhiyun The controller expects two clocks, the clock used for the AXI interface and 8*4882a593Smuzhiyun the clock used as the sampling rate reference clock sample. 9*4882a593Smuzhiyun - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample 10*4882a593Smuzhiyun rate reference clock. 11*4882a593Smuzhiyun - dmas: Pairs of phandle and specifier for the DMA channel that is used by 12*4882a593Smuzhiyun the core. The core expects one dma channel for transmit. 13*4882a593Smuzhiyun - dma-names : Must be "tx" 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunFor more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties 16*4882a593Smuzhiyunplease check: 17*4882a593Smuzhiyun * resource-names.txt 18*4882a593Smuzhiyun * clock/clock-bindings.txt 19*4882a593Smuzhiyun * dma/dma.txt 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun spdif: spdif@77400000 { 24*4882a593Smuzhiyun compatible = "adi,axi-spdif-tx-1.00.a"; 25*4882a593Smuzhiyun reg = <0x77600000 0x1000>; 26*4882a593Smuzhiyun clocks = <&clk 15>, <&audio_clock>; 27*4882a593Smuzhiyun clock-names = "axi", "ref"; 28*4882a593Smuzhiyun dmas = <&ps7_dma 0>; 29*4882a593Smuzhiyun dma-names = "tx"; 30*4882a593Smuzhiyun }; 31