1*4882a593SmuzhiyunADI AXI-I2S controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe core can be generated with transmit (playback), only receive 4*4882a593Smuzhiyun(capture) or both directions enabled. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun - compatible : Must be "adi,axi-i2s-1.00.a" 8*4882a593Smuzhiyun - reg : Must contain I2S core's registers location and length 9*4882a593Smuzhiyun - clocks : Pairs of phandle and specifier referencing the controller's clocks. 10*4882a593Smuzhiyun The controller expects two clocks, the clock used for the AXI interface and 11*4882a593Smuzhiyun the clock used as the sampling rate reference clock sample. 12*4882a593Smuzhiyun - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample 13*4882a593Smuzhiyun rate reference clock. 14*4882a593Smuzhiyun - dmas: Pairs of phandle and specifier for the DMA channels that are used by 15*4882a593Smuzhiyun the core. The core expects two dma channels if both transmit and receive are 16*4882a593Smuzhiyun enabled, one channel otherwise. 17*4882a593Smuzhiyun - dma-names : "tx" for the transmit channel, "rx" for the receive channel. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunFor more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties 20*4882a593Smuzhiyunplease check: 21*4882a593Smuzhiyun * resource-names.txt 22*4882a593Smuzhiyun * clock/clock-bindings.txt 23*4882a593Smuzhiyun * dma/dma.txt 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun i2s: i2s@77600000 { 28*4882a593Smuzhiyun compatible = "adi,axi-i2s-1.00.a"; 29*4882a593Smuzhiyun reg = <0x77600000 0x1000>; 30*4882a593Smuzhiyun clocks = <&clk 15>, <&audio_clock>; 31*4882a593Smuzhiyun clock-names = "axi", "ref"; 32*4882a593Smuzhiyun dmas = <&ps7_dma 0>, <&ps7_dma 1>; 33*4882a593Smuzhiyun dma-names = "tx", "rx"; 34*4882a593Smuzhiyun }; 35