1*4882a593SmuzhiyunQualcomm Shared Memory State Machine 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Shared Memory State Machine facilitates broadcasting of single bit state 4*4882a593Smuzhiyuninformation between the processors in a Qualcomm SoC. Each processor is 5*4882a593Smuzhiyunassigned 32 bits of state that can be modified. A processor can through a 6*4882a593Smuzhiyunmatrix of bitmaps signal subscription of notifications upon changes to a 7*4882a593Smuzhiyuncertain bit owned by a certain remote processor. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: 10*4882a593Smuzhiyun Usage: required 11*4882a593Smuzhiyun Value type: <string> 12*4882a593Smuzhiyun Definition: must be one of: 13*4882a593Smuzhiyun "qcom,smsm" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- qcom,ipc-N: 16*4882a593Smuzhiyun Usage: required 17*4882a593Smuzhiyun Value type: <prop-encoded-array> 18*4882a593Smuzhiyun Definition: three entries specifying the outgoing ipc bit used for 19*4882a593Smuzhiyun signaling the N:th remote processor 20*4882a593Smuzhiyun - phandle to a syscon node representing the apcs registers 21*4882a593Smuzhiyun - u32 representing offset to the register within the syscon 22*4882a593Smuzhiyun - u32 representing the ipc bit within the register 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- qcom,local-host: 25*4882a593Smuzhiyun Usage: optional 26*4882a593Smuzhiyun Value type: <u32> 27*4882a593Smuzhiyun Definition: identifier of the local processor in the list of hosts, or 28*4882a593Smuzhiyun in other words specifier of the column in the subscription 29*4882a593Smuzhiyun matrix representing the local processor 30*4882a593Smuzhiyun defaults to host 0 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- #address-cells: 33*4882a593Smuzhiyun Usage: required 34*4882a593Smuzhiyun Value type: <u32> 35*4882a593Smuzhiyun Definition: must be 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- #size-cells: 38*4882a593Smuzhiyun Usage: required 39*4882a593Smuzhiyun Value type: <u32> 40*4882a593Smuzhiyun Definition: must be 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun= SUBNODES 43*4882a593SmuzhiyunEach processor's state bits are described by a subnode of the smsm device node. 44*4882a593SmuzhiyunNodes can either be flagged as an interrupt-controller to denote a remote 45*4882a593Smuzhiyunprocessor's state bits or the local processors bits. The node names are not 46*4882a593Smuzhiyunimportant. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun- reg: 49*4882a593Smuzhiyun Usage: required 50*4882a593Smuzhiyun Value type: <u32> 51*4882a593Smuzhiyun Definition: specifies the offset, in words, of the first bit for this 52*4882a593Smuzhiyun entry 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- #qcom,smem-state-cells: 55*4882a593Smuzhiyun Usage: required for local entry 56*4882a593Smuzhiyun Value type: <u32> 57*4882a593Smuzhiyun Definition: must be 1 - denotes bit number 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun- interrupt-controller: 60*4882a593Smuzhiyun Usage: required for remote entries 61*4882a593Smuzhiyun Value type: <empty> 62*4882a593Smuzhiyun Definition: marks the entry as a interrupt-controller and the state bits 63*4882a593Smuzhiyun to belong to a remote processor 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun- #interrupt-cells: 66*4882a593Smuzhiyun Usage: required for remote entries 67*4882a593Smuzhiyun Value type: <u32> 68*4882a593Smuzhiyun Definition: must be 2 - denotes bit number and IRQ flags 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun- interrupts: 71*4882a593Smuzhiyun Usage: required for remote entries 72*4882a593Smuzhiyun Value type: <prop-encoded-array> 73*4882a593Smuzhiyun Definition: one entry specifying remote IRQ used by the remote processor 74*4882a593Smuzhiyun to signal changes of its state bits 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun= EXAMPLE 78*4882a593SmuzhiyunThe following example shows the SMEM setup for controlling properties of the 79*4882a593Smuzhiyunwireless processor, defined from the 8974 apps processor's point-of-view. It 80*4882a593Smuzhiyunencompasses one outbound entry and the outgoing interrupt for the wireless 81*4882a593Smuzhiyunprocessor. 82*4882a593Smuzhiyun 83*4882a593Smuzhiyunsmsm { 84*4882a593Smuzhiyun compatible = "qcom,smsm"; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun qcom,ipc-3 = <&apcs 8 19>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun apps_smsm: apps@0 { 92*4882a593Smuzhiyun reg = <0>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #qcom,smem-state-cells = <1>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun wcnss_smsm: wcnss@7 { 98*4882a593Smuzhiyun reg = <7>; 99*4882a593Smuzhiyun interrupts = <0 144 1>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun interrupt-controller; 102*4882a593Smuzhiyun #interrupt-cells = <2>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun}; 105