1*4882a593SmuzhiyunMediaTek PMIC Wrapper Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis document describes the binding for the MediaTek PMIC wrapper. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunOn MediaTek SoCs the PMIC is connected via SPI. The SPI master interface 6*4882a593Smuzhiyunis not directly visible to the CPU, but only through the PMIC wrapper 7*4882a593Smuzhiyuninside the SoC. The communication between the SoC and the PMIC can 8*4882a593Smuzhiyunoptionally be encrypted. Also a non standard Dual IO SPI mode can be 9*4882a593Smuzhiyunused to increase speed. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunIP Pairing 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunon MT8135 the pins of some SoC internal peripherals can be on the PMIC. 14*4882a593SmuzhiyunThe signals of these pins are routed over the SPI bus using the pwrap 15*4882a593Smuzhiyunbridge. In the binding description below the properties needed for bridging 16*4882a593Smuzhiyunare marked with "IP Pairing". These are optional on SoCs which do not support 17*4882a593SmuzhiyunIP Pairing 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRequired properties in pwrap device node. 20*4882a593Smuzhiyun- compatible: 21*4882a593Smuzhiyun "mediatek,mt2701-pwrap" for MT2701/7623 SoCs 22*4882a593Smuzhiyun "mediatek,mt6765-pwrap" for MT6765 SoCs 23*4882a593Smuzhiyun "mediatek,mt6779-pwrap" for MT6779 SoCs 24*4882a593Smuzhiyun "mediatek,mt6797-pwrap" for MT6797 SoCs 25*4882a593Smuzhiyun "mediatek,mt7622-pwrap" for MT7622 SoCs 26*4882a593Smuzhiyun "mediatek,mt8135-pwrap" for MT8135 SoCs 27*4882a593Smuzhiyun "mediatek,mt8173-pwrap" for MT8173 SoCs 28*4882a593Smuzhiyun "mediatek,mt8183-pwrap" for MT8183 SoCs 29*4882a593Smuzhiyun "mediatek,mt8516-pwrap" for MT8516 SoCs 30*4882a593Smuzhiyun- interrupts: IRQ for pwrap in SOC 31*4882a593Smuzhiyun- reg-names: Must include the following entries: 32*4882a593Smuzhiyun "pwrap": Main registers base 33*4882a593Smuzhiyun "pwrap-bridge": bridge base (IP Pairing) 34*4882a593Smuzhiyun- reg: Must contain an entry for each entry in reg-names. 35*4882a593Smuzhiyun- reset-names: Must include the following entries: 36*4882a593Smuzhiyun "pwrap" 37*4882a593Smuzhiyun "pwrap-bridge" (IP Pairing) 38*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 39*4882a593Smuzhiyun- clock-names: Must include the following entries: 40*4882a593Smuzhiyun "spi": SPI bus clock 41*4882a593Smuzhiyun "wrap": Main module clock 42*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunOptional properities: 45*4882a593Smuzhiyun- pmic: Using either MediaTek PMIC MFD as the child device of pwrap 46*4882a593Smuzhiyun See the following for child node definitions: 47*4882a593Smuzhiyun Documentation/devicetree/bindings/mfd/mt6397.txt 48*4882a593Smuzhiyun or the regulator-only device as the child device of pwrap, such as MT6380. 49*4882a593Smuzhiyun See the following definitions for such kinds of devices. 50*4882a593Smuzhiyun Documentation/devicetree/bindings/regulator/mt6380-regulator.txt 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExample: 53*4882a593Smuzhiyun pwrap: pwrap@1000f000 { 54*4882a593Smuzhiyun compatible = "mediatek,mt8135-pwrap"; 55*4882a593Smuzhiyun reg = <0 0x1000f000 0 0x1000>, 56*4882a593Smuzhiyun <0 0x11017000 0 0x1000>; 57*4882a593Smuzhiyun reg-names = "pwrap", "pwrap-bridge"; 58*4882a593Smuzhiyun interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 59*4882a593Smuzhiyun resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, 60*4882a593Smuzhiyun <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; 61*4882a593Smuzhiyun reset-names = "pwrap", "pwrap-bridge"; 62*4882a593Smuzhiyun clocks = <&clk26m>, <&clk26m>; 63*4882a593Smuzhiyun clock-names = "spi", "wrap"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pmic { 66*4882a593Smuzhiyun compatible = "mediatek,mt6397"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69