1*4882a593Smuzhiyun* Run Control and Power Management 2*4882a593Smuzhiyun------------------------------------------- 3*4882a593SmuzhiyunThe RCPM performs all device-level tasks associated with device run control 4*4882a593Smuzhiyunand power management. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properites: 7*4882a593Smuzhiyun - reg : Offset and length of the register set of the RCPM block. 8*4882a593Smuzhiyun - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the 9*4882a593Smuzhiyun fsl,rcpm-wakeup property. 10*4882a593Smuzhiyun - compatible : Must contain a chip-specific RCPM block compatible string 11*4882a593Smuzhiyun and (if applicable) may contain a chassis-version RCPM compatible 12*4882a593Smuzhiyun string. Chip-specific strings are of the form "fsl,<chip>-rcpm", 13*4882a593Smuzhiyun such as: 14*4882a593Smuzhiyun * "fsl,p2041-rcpm" 15*4882a593Smuzhiyun * "fsl,p5020-rcpm" 16*4882a593Smuzhiyun * "fsl,t4240-rcpm" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>", 19*4882a593Smuzhiyun such as: 20*4882a593Smuzhiyun * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm 21*4882a593Smuzhiyun * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm 22*4882a593Smuzhiyun * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm 23*4882a593Smuzhiyun * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunAll references to "1.0" and "2.0" refer to the QorIQ chassis version to 26*4882a593Smuzhiyunwhich the chip complies. 27*4882a593SmuzhiyunChassis Version Example Chips 28*4882a593Smuzhiyun--------------- ------------------------------- 29*4882a593Smuzhiyun1.0 p4080, p5020, p5040, p2041, p3041 30*4882a593Smuzhiyun2.0 t4240, b4860, b4420 31*4882a593Smuzhiyun2.1 t1040, 32*4882a593Smuzhiyun2.1+ ls1021a, ls1012a, ls1043a, ls1046a 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunOptional properties: 35*4882a593Smuzhiyun - little-endian : RCPM register block is Little Endian. Without it RCPM 36*4882a593Smuzhiyun will be Big Endian (default case). 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExample: 39*4882a593SmuzhiyunThe RCPM node for T4240: 40*4882a593Smuzhiyun rcpm: global-utilities@e2000 { 41*4882a593Smuzhiyun compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; 42*4882a593Smuzhiyun reg = <0xe2000 0x1000>; 43*4882a593Smuzhiyun #fsl,rcpm-wakeup-cells = <2>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun* Freescale RCPM Wakeup Source Device Tree Bindings 47*4882a593Smuzhiyun------------------------------------------- 48*4882a593SmuzhiyunRequired fsl,rcpm-wakeup property should be added to a device node if the device 49*4882a593Smuzhiyuncan be used as a wakeup source. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR 52*4882a593Smuzhiyun register cells. The number of IPPDEXPCR register cells is defined in 53*4882a593Smuzhiyun "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is 54*4882a593Smuzhiyun the bit mask that should be set in IPPDEXPCR0, and the second register 55*4882a593Smuzhiyun cell is for IPPDEXPCR1, and so on. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a 58*4882a593Smuzhiyun mechanism for keeping certain blocks awake during STANDBY and MEM, in 59*4882a593Smuzhiyun order to use them as wake-up sources. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunExample: 62*4882a593Smuzhiyun lpuart0: serial@2950000 { 63*4882a593Smuzhiyun compatible = "fsl,ls1021a-lpuart"; 64*4882a593Smuzhiyun reg = <0x0 0x2950000 0x0 0x1000>; 65*4882a593Smuzhiyun interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 66*4882a593Smuzhiyun clocks = <&sysclk>; 67*4882a593Smuzhiyun clock-names = "ipg"; 68*4882a593Smuzhiyun fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>; 69*4882a593Smuzhiyun }; 70