1*4882a593SmuzhiyunDevice Tree bindings for Marvell PMU 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: value should be "marvell,dove-pmu". 5*4882a593Smuzhiyun May also include "simple-bus" if there are child devices, in which 6*4882a593Smuzhiyun case the ranges node is required. 7*4882a593Smuzhiyun - reg: two base addresses and sizes of the PM controller and PMU. 8*4882a593Smuzhiyun - interrupts: single interrupt number for the PMU interrupt 9*4882a593Smuzhiyun - interrupt-controller: must be specified as the PMU itself is an 10*4882a593Smuzhiyun interrupt controller. 11*4882a593Smuzhiyun - #interrupt-cells: must be 1. 12*4882a593Smuzhiyun - #reset-cells: must be 1. 13*4882a593Smuzhiyun - domains: sub-node containing domain descriptions 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun - ranges: defines the address mapping for child devices, as per the 17*4882a593Smuzhiyun standard property of this name. Required when compatible includes 18*4882a593Smuzhiyun "simple-bus". 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunPower domain descriptions are listed as child nodes of the "domains" 21*4882a593Smuzhiyunsub-node. Each domain has the following properties: 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunRequired properties: 24*4882a593Smuzhiyun - #power-domain-cells: must be 0. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun - marvell,pmu_pwr_mask: specifies the mask value for PMU power register 28*4882a593Smuzhiyun - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register 29*4882a593Smuzhiyun - resets: points to the reset manager (PMU node) and reset index. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun pmu: power-management@d0000 { 34*4882a593Smuzhiyun compatible = "marvell,dove-pmu"; 35*4882a593Smuzhiyun reg = <0xd0000 0x8000>, <0xd8000 0x8000>; 36*4882a593Smuzhiyun interrupts = <33>; 37*4882a593Smuzhiyun interrupt-controller; 38*4882a593Smuzhiyun #interrupt-cells = <1>; 39*4882a593Smuzhiyun #reset-cells = <1>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun domains { 42*4882a593Smuzhiyun vpu_domain: vpu-domain { 43*4882a593Smuzhiyun #power-domain-cells = <0>; 44*4882a593Smuzhiyun marvell,pmu_pwr_mask = <0x00000008>; 45*4882a593Smuzhiyun marvell,pmu_iso_mask = <0x00000001>; 46*4882a593Smuzhiyun resets = <&pmu 16>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun gpu_domain: gpu-domain { 50*4882a593Smuzhiyun #power-domain-cells = <0>; 51*4882a593Smuzhiyun marvell,pmu_pwr_mask = <0x00000004>; 52*4882a593Smuzhiyun marvell,pmu_iso_mask = <0x00000002>; 53*4882a593Smuzhiyun resets = <&pmu 18>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57