1*4882a593SmuzhiyunXilinx Axi Uartlite controller Device Tree Bindings 2*4882a593Smuzhiyun--------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Can be either of 6*4882a593Smuzhiyun "xlnx,xps-uartlite-1.00.a" 7*4882a593Smuzhiyun "xlnx,opb-uartlite-1.00.b" 8*4882a593Smuzhiyun- reg : Physical base address and size of the Axi Uartlite 9*4882a593Smuzhiyun registers map. 10*4882a593Smuzhiyun- interrupts : Should contain the UART controller interrupt. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- port-number : Set Uart port number 14*4882a593Smuzhiyun- clock-names : Should be "s_axi_aclk" 15*4882a593Smuzhiyun- clocks : Input clock specifier. Refer to common clock bindings. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyunserial@800c0000 { 19*4882a593Smuzhiyun compatible = "xlnx,xps-uartlite-1.00.a"; 20*4882a593Smuzhiyun reg = <0x0 0x800c0000 0x10000>; 21*4882a593Smuzhiyun interrupts = <0x0 0x6e 0x1>; 22*4882a593Smuzhiyun port-number = <0>; 23*4882a593Smuzhiyun}; 24