1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2019 Unisoc Inc. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/serial/sprd-uart.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Spreadtrum serial UART 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Orson Zhai <orsonzhai@gmail.com> 12*4882a593Smuzhiyun - Baolin Wang <baolin.wang7@gmail.com> 13*4882a593Smuzhiyun - Chunyan Zhang <zhang.lyra@gmail.com> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - enum: 20*4882a593Smuzhiyun - sprd,sc9860-uart 21*4882a593Smuzhiyun - sprd,sc9863a-uart 22*4882a593Smuzhiyun - const: sprd,sc9836-uart 23*4882a593Smuzhiyun - const: sprd,sc9836-uart 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun interrupts: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clocks: 32*4882a593Smuzhiyun minItems: 1 33*4882a593Smuzhiyun maxItems: 3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock-names: 36*4882a593Smuzhiyun description: | 37*4882a593Smuzhiyun "enable" for UART module enable clock, "uart" for UART clock, "source" 38*4882a593Smuzhiyun for UART source (parent) clock. 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - const: enable 41*4882a593Smuzhiyun - const: uart 42*4882a593Smuzhiyun - const: source 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun dmas: 45*4882a593Smuzhiyun minItems: 1 46*4882a593Smuzhiyun maxItems: 2 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun dma-names: 49*4882a593Smuzhiyun minItems: 1 50*4882a593Smuzhiyun items: 51*4882a593Smuzhiyun - const: rx 52*4882a593Smuzhiyun - const: tx 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunrequired: 55*4882a593Smuzhiyun - compatible 56*4882a593Smuzhiyun - reg 57*4882a593Smuzhiyun - interrupts 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunadditionalProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunexamples: 62*4882a593Smuzhiyun - | 63*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 64*4882a593Smuzhiyun serial@0 { 65*4882a593Smuzhiyun compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; 66*4882a593Smuzhiyun reg = <0x0 0x100>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 68*4882a593Smuzhiyun dma-names = "rx", "tx"; 69*4882a593Smuzhiyun dmas = <&ap_dma 19>, <&ap_dma 20>; 70*4882a593Smuzhiyun clock-names = "enable", "uart", "source"; 71*4882a593Smuzhiyun clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun... 75