1*4882a593Smuzhiyun* Universal Asynchronous Receiver/Transmitter (UART) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun- compatible: "rockchip,rk_serial" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Compatibility with all rk28xx rk29xx rk30xx rk31xx SOCs. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg: The base address of the UART register bank. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- interrupts: A single interrupt specifier. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- id: port line, determine the ttySx 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- use-dma-rx: enable dma receive 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- use-dma-tx: enable dma tramsmit 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyunuart0: serial@10124000 { 19*4882a593Smuzhiyun compatible = "rockchip,rk_serial"; 20*4882a593Smuzhiyun reg = <0x10124000 0x100>; 21*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 22*4882a593Smuzhiyun clock-frequency = <24000000>; 23*4882a593Smuzhiyun id = <0>; 24*4882a593Smuzhiyun use-dma-rx; 25*4882a593Smuzhiyun use-dma-tx; 26*4882a593Smuzhiyun status = "disabled"; 27*4882a593Smuzhiyun }; 28