1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas Serial Communication Interface with FIFO (SCIF) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: serial.yaml# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - enum: 20*4882a593Smuzhiyun - renesas,scif-r7s72100 # RZ/A1H 21*4882a593Smuzhiyun - const: renesas,scif # generic SCIF compatible UART 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - items: 24*4882a593Smuzhiyun - enum: 25*4882a593Smuzhiyun - renesas,scif-r7s9210 # RZ/A2 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun - items: 28*4882a593Smuzhiyun - enum: 29*4882a593Smuzhiyun - renesas,scif-r8a7778 # R-Car M1 30*4882a593Smuzhiyun - renesas,scif-r8a7779 # R-Car H1 31*4882a593Smuzhiyun - const: renesas,rcar-gen1-scif # R-Car Gen1 32*4882a593Smuzhiyun - const: renesas,scif # generic SCIF compatible UART 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun - items: 35*4882a593Smuzhiyun - enum: 36*4882a593Smuzhiyun - renesas,scif-r8a7742 # RZ/G1H 37*4882a593Smuzhiyun - renesas,scif-r8a7743 # RZ/G1M 38*4882a593Smuzhiyun - renesas,scif-r8a7744 # RZ/G1N 39*4882a593Smuzhiyun - renesas,scif-r8a7745 # RZ/G1E 40*4882a593Smuzhiyun - renesas,scif-r8a77470 # RZ/G1C 41*4882a593Smuzhiyun - renesas,scif-r8a7790 # R-Car H2 42*4882a593Smuzhiyun - renesas,scif-r8a7791 # R-Car M2-W 43*4882a593Smuzhiyun - renesas,scif-r8a7792 # R-Car V2H 44*4882a593Smuzhiyun - renesas,scif-r8a7793 # R-Car M2-N 45*4882a593Smuzhiyun - renesas,scif-r8a7794 # R-Car E2 46*4882a593Smuzhiyun - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1 47*4882a593Smuzhiyun - const: renesas,scif # generic SCIF compatible UART 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun - items: 50*4882a593Smuzhiyun - enum: 51*4882a593Smuzhiyun - renesas,scif-r8a774a1 # RZ/G2M 52*4882a593Smuzhiyun - renesas,scif-r8a774b1 # RZ/G2N 53*4882a593Smuzhiyun - renesas,scif-r8a774c0 # RZ/G2E 54*4882a593Smuzhiyun - renesas,scif-r8a774e1 # RZ/G2H 55*4882a593Smuzhiyun - renesas,scif-r8a7795 # R-Car H3 56*4882a593Smuzhiyun - renesas,scif-r8a7796 # R-Car M3-W 57*4882a593Smuzhiyun - renesas,scif-r8a77961 # R-Car M3-W+ 58*4882a593Smuzhiyun - renesas,scif-r8a77965 # R-Car M3-N 59*4882a593Smuzhiyun - renesas,scif-r8a77970 # R-Car V3M 60*4882a593Smuzhiyun - renesas,scif-r8a77980 # R-Car V3H 61*4882a593Smuzhiyun - renesas,scif-r8a77990 # R-Car E3 62*4882a593Smuzhiyun - renesas,scif-r8a77995 # R-Car D3 63*4882a593Smuzhiyun - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 64*4882a593Smuzhiyun - const: renesas,scif # generic SCIF compatible UART 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg: 67*4882a593Smuzhiyun maxItems: 1 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun interrupts: 70*4882a593Smuzhiyun oneOf: 71*4882a593Smuzhiyun - items: 72*4882a593Smuzhiyun - description: A combined interrupt 73*4882a593Smuzhiyun - items: 74*4882a593Smuzhiyun - description: Error interrupt 75*4882a593Smuzhiyun - description: Receive buffer full interrupt 76*4882a593Smuzhiyun - description: Transmit buffer empty interrupt 77*4882a593Smuzhiyun - description: Transmit End interrupt 78*4882a593Smuzhiyun - items: 79*4882a593Smuzhiyun - description: Error interrupt 80*4882a593Smuzhiyun - description: Receive buffer full interrupt 81*4882a593Smuzhiyun - description: Transmit buffer empty interrupt 82*4882a593Smuzhiyun - description: Break interrupt 83*4882a593Smuzhiyun - description: Data Ready interrupt 84*4882a593Smuzhiyun - description: Transmit End interrupt 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun interrupt-names: 87*4882a593Smuzhiyun oneOf: 88*4882a593Smuzhiyun - items: 89*4882a593Smuzhiyun - const: eri 90*4882a593Smuzhiyun - const: rxi 91*4882a593Smuzhiyun - const: txi 92*4882a593Smuzhiyun - const: tei 93*4882a593Smuzhiyun - items: 94*4882a593Smuzhiyun - const: eri 95*4882a593Smuzhiyun - const: rxi 96*4882a593Smuzhiyun - const: txi 97*4882a593Smuzhiyun - const: bri 98*4882a593Smuzhiyun - const: dri 99*4882a593Smuzhiyun - const: tei 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun clocks: 102*4882a593Smuzhiyun minItems: 1 103*4882a593Smuzhiyun maxItems: 4 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun clock-names: 106*4882a593Smuzhiyun minItems: 1 107*4882a593Smuzhiyun maxItems: 4 108*4882a593Smuzhiyun items: 109*4882a593Smuzhiyun enum: 110*4882a593Smuzhiyun - fck # UART functional clock 111*4882a593Smuzhiyun - sck # optional external clock input 112*4882a593Smuzhiyun - brg_int # optional internal clock source for BRG frequency divider 113*4882a593Smuzhiyun - scif_clk # optional external clock source for BRG frequency divider 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun power-domains: 116*4882a593Smuzhiyun maxItems: 1 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun resets: 119*4882a593Smuzhiyun maxItems: 1 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun dmas: 122*4882a593Smuzhiyun description: 123*4882a593Smuzhiyun Must contain a list of pairs of references to DMA specifiers, one for 124*4882a593Smuzhiyun transmission, and one for reception. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun dma-names: 127*4882a593Smuzhiyun minItems: 2 128*4882a593Smuzhiyun maxItems: 4 129*4882a593Smuzhiyun items: 130*4882a593Smuzhiyun enum: 131*4882a593Smuzhiyun - tx 132*4882a593Smuzhiyun - rx 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunrequired: 135*4882a593Smuzhiyun - compatible 136*4882a593Smuzhiyun - reg 137*4882a593Smuzhiyun - interrupts 138*4882a593Smuzhiyun - clocks 139*4882a593Smuzhiyun - clock-names 140*4882a593Smuzhiyun - power-domains 141*4882a593Smuzhiyun 142*4882a593Smuzhiyunif: 143*4882a593Smuzhiyun properties: 144*4882a593Smuzhiyun compatible: 145*4882a593Smuzhiyun contains: 146*4882a593Smuzhiyun enum: 147*4882a593Smuzhiyun - renesas,rcar-gen2-scif 148*4882a593Smuzhiyun - renesas,rcar-gen3-scif 149*4882a593Smuzhiyunthen: 150*4882a593Smuzhiyun required: 151*4882a593Smuzhiyun - resets 152*4882a593Smuzhiyun 153*4882a593SmuzhiyununevaluatedProperties: false 154*4882a593Smuzhiyun 155*4882a593Smuzhiyunexamples: 156*4882a593Smuzhiyun - | 157*4882a593Smuzhiyun #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 158*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 159*4882a593Smuzhiyun #include <dt-bindings/power/r8a7791-sysc.h> 160*4882a593Smuzhiyun aliases { 161*4882a593Smuzhiyun serial0 = &scif0; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun scif0: serial@e6e60000 { 165*4882a593Smuzhiyun compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 166*4882a593Smuzhiyun "renesas,scif"; 167*4882a593Smuzhiyun reg = <0xe6e60000 64>; 168*4882a593Smuzhiyun interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 169*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, 170*4882a593Smuzhiyun <&scif_clk>; 171*4882a593Smuzhiyun clock-names = "fck", "brg_int", "scif_clk"; 172*4882a593Smuzhiyun dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; 173*4882a593Smuzhiyun dma-names = "tx", "rx", "tx", "rx"; 174*4882a593Smuzhiyun power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 175*4882a593Smuzhiyun resets = <&cpg 721>; 176*4882a593Smuzhiyun }; 177