1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas High Speed Serial Communication Interface with FIFO (HSCIF) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: serial.yaml# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - enum: 20*4882a593Smuzhiyun - renesas,hscif-r8a7778 # R-Car M1 21*4882a593Smuzhiyun - renesas,hscif-r8a7779 # R-Car H1 22*4882a593Smuzhiyun - const: renesas,rcar-gen1-hscif # R-Car Gen1 23*4882a593Smuzhiyun - const: renesas,hscif # generic HSCIF compatible UART 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - items: 26*4882a593Smuzhiyun - enum: 27*4882a593Smuzhiyun - renesas,hscif-r8a7742 # RZ/G1H 28*4882a593Smuzhiyun - renesas,hscif-r8a7743 # RZ/G1M 29*4882a593Smuzhiyun - renesas,hscif-r8a7744 # RZ/G1N 30*4882a593Smuzhiyun - renesas,hscif-r8a7745 # RZ/G1E 31*4882a593Smuzhiyun - renesas,hscif-r8a77470 # RZ/G1C 32*4882a593Smuzhiyun - renesas,hscif-r8a7790 # R-Car H2 33*4882a593Smuzhiyun - renesas,hscif-r8a7791 # R-Car M2-W 34*4882a593Smuzhiyun - renesas,hscif-r8a7792 # R-Car V2H 35*4882a593Smuzhiyun - renesas,hscif-r8a7793 # R-Car M2-N 36*4882a593Smuzhiyun - renesas,hscif-r8a7794 # R-Car E2 37*4882a593Smuzhiyun - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1 38*4882a593Smuzhiyun - const: renesas,hscif # generic HSCIF compatible UART 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun - items: 41*4882a593Smuzhiyun - enum: 42*4882a593Smuzhiyun - renesas,hscif-r8a774a1 # RZ/G2M 43*4882a593Smuzhiyun - renesas,hscif-r8a774b1 # RZ/G2N 44*4882a593Smuzhiyun - renesas,hscif-r8a774c0 # RZ/G2E 45*4882a593Smuzhiyun - renesas,hscif-r8a774e1 # RZ/G2H 46*4882a593Smuzhiyun - renesas,hscif-r8a7795 # R-Car H3 47*4882a593Smuzhiyun - renesas,hscif-r8a7796 # R-Car M3-W 48*4882a593Smuzhiyun - renesas,hscif-r8a77961 # R-Car M3-W+ 49*4882a593Smuzhiyun - renesas,hscif-r8a77965 # R-Car M3-N 50*4882a593Smuzhiyun - renesas,hscif-r8a77970 # R-Car V3M 51*4882a593Smuzhiyun - renesas,hscif-r8a77980 # R-Car V3H 52*4882a593Smuzhiyun - renesas,hscif-r8a77990 # R-Car E3 53*4882a593Smuzhiyun - renesas,hscif-r8a77995 # R-Car D3 54*4882a593Smuzhiyun - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 55*4882a593Smuzhiyun - const: renesas,hscif # generic HSCIF compatible UART 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun reg: 58*4882a593Smuzhiyun maxItems: 1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun interrupts: 61*4882a593Smuzhiyun maxItems: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun clocks: 64*4882a593Smuzhiyun minItems: 1 65*4882a593Smuzhiyun maxItems: 4 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clock-names: 68*4882a593Smuzhiyun minItems: 1 69*4882a593Smuzhiyun maxItems: 4 70*4882a593Smuzhiyun items: 71*4882a593Smuzhiyun enum: 72*4882a593Smuzhiyun - fck # UART functional clock 73*4882a593Smuzhiyun - hsck # optional external clock input 74*4882a593Smuzhiyun - brg_int # optional internal clock source for BRG frequency divider 75*4882a593Smuzhiyun - scif_clk # optional external clock source for BRG frequency divider 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun power-domains: 78*4882a593Smuzhiyun maxItems: 1 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun resets: 81*4882a593Smuzhiyun maxItems: 1 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun dmas: 84*4882a593Smuzhiyun description: 85*4882a593Smuzhiyun Must contain a list of pairs of references to DMA specifiers, one for 86*4882a593Smuzhiyun transmission, and one for reception. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun dma-names: 89*4882a593Smuzhiyun minItems: 2 90*4882a593Smuzhiyun maxItems: 4 91*4882a593Smuzhiyun items: 92*4882a593Smuzhiyun enum: 93*4882a593Smuzhiyun - tx 94*4882a593Smuzhiyun - rx 95*4882a593Smuzhiyun 96*4882a593Smuzhiyunrequired: 97*4882a593Smuzhiyun - compatible 98*4882a593Smuzhiyun - reg 99*4882a593Smuzhiyun - interrupts 100*4882a593Smuzhiyun - clocks 101*4882a593Smuzhiyun - clock-names 102*4882a593Smuzhiyun - power-domains 103*4882a593Smuzhiyun 104*4882a593SmuzhiyununevaluatedProperties: false 105*4882a593Smuzhiyun 106*4882a593Smuzhiyunif: 107*4882a593Smuzhiyun properties: 108*4882a593Smuzhiyun compatible: 109*4882a593Smuzhiyun contains: 110*4882a593Smuzhiyun enum: 111*4882a593Smuzhiyun - renesas,rcar-gen2-hscif 112*4882a593Smuzhiyun - renesas,rcar-gen3-hscif 113*4882a593Smuzhiyunthen: 114*4882a593Smuzhiyun required: 115*4882a593Smuzhiyun - resets 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunexamples: 118*4882a593Smuzhiyun - | 119*4882a593Smuzhiyun #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 120*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 121*4882a593Smuzhiyun #include <dt-bindings/power/r8a7795-sysc.h> 122*4882a593Smuzhiyun aliases { 123*4882a593Smuzhiyun serial1 = &hscif1; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun hscif1: serial@e6550000 { 127*4882a593Smuzhiyun compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", 128*4882a593Smuzhiyun "renesas,hscif"; 129*4882a593Smuzhiyun reg = <0xe6550000 96>; 130*4882a593Smuzhiyun interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 131*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, 132*4882a593Smuzhiyun <&scif_clk>; 133*4882a593Smuzhiyun clock-names = "fck", "brg_int", "scif_clk"; 134*4882a593Smuzhiyun dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; 135*4882a593Smuzhiyun dma-names = "tx", "rx", "tx", "rx"; 136*4882a593Smuzhiyun power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 137*4882a593Smuzhiyun resets = <&cpg 519>; 138*4882a593Smuzhiyun uart-has-rtscts; 139*4882a593Smuzhiyun }; 140