1*4882a593Smuzhiyun* MSM Serial UARTDM 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe MSM serial UARTDM hardware is designed for high-speed use cases where the 4*4882a593Smuzhiyuntransmit and/or receive channels can be offloaded to a dma-engine. From a 5*4882a593Smuzhiyunsoftware perspective it's mostly compatible with the MSM serial UART except 6*4882a593Smuzhiyunthat it supports reading and writing multiple characters at a time. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: Should contain at least "qcom,msm-uartdm". 10*4882a593Smuzhiyun A more specific property should be specified as follows depending 11*4882a593Smuzhiyun on the version: 12*4882a593Smuzhiyun "qcom,msm-uartdm-v1.1" 13*4882a593Smuzhiyun "qcom,msm-uartdm-v1.2" 14*4882a593Smuzhiyun "qcom,msm-uartdm-v1.3" 15*4882a593Smuzhiyun "qcom,msm-uartdm-v1.4" 16*4882a593Smuzhiyun- reg: Should contain UART register locations and lengths. The first 17*4882a593Smuzhiyun register shall specify the main control registers. An optional second 18*4882a593Smuzhiyun register location shall specify the GSBI control region. 19*4882a593Smuzhiyun "qcom,msm-uartdm-v1.3" is the only compatible value that might 20*4882a593Smuzhiyun need the GSBI control region. 21*4882a593Smuzhiyun- interrupts: Should contain UART interrupt. 22*4882a593Smuzhiyun- clocks: Should contain the core clock and the AHB clock. 23*4882a593Smuzhiyun- clock-names: Should be "core" for the core clock and "iface" for the 24*4882a593Smuzhiyun AHB clock. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun- dmas: Should contain dma specifiers for transmit and receive channels 28*4882a593Smuzhiyun- dma-names: Should contain "tx" for transmit and "rx" for receive channels 29*4882a593Smuzhiyun- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be 30*4882a593Smuzhiyun used with TX DMA channel. Required when using DMA for transmission 31*4882a593Smuzhiyun with UARTDM v1.3 and below. 32*4882a593Smuzhiyun- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be 33*4882a593Smuzhiyun used with RX DMA channel. Required when using DMA for reception 34*4882a593Smuzhiyun with UARTDM v1.3 and below. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunNote: Aliases may be defined to ensure the correct ordering of the UARTs. 37*4882a593SmuzhiyunThe alias serialN will result in the UART being assigned port N. If any 38*4882a593SmuzhiyunserialN alias exists, then an alias must exist for each enabled UART. The 39*4882a593SmuzhiyunserialN aliases should be in a .dts file instead of in a .dtsi file. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExamples: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun- A uartdm v1.4 device with dma capabilities. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun serial@f991e000 { 46*4882a593Smuzhiyun compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 47*4882a593Smuzhiyun reg = <0xf991e000 0x1000>; 48*4882a593Smuzhiyun interrupts = <0 108 0x0>; 49*4882a593Smuzhiyun clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; 50*4882a593Smuzhiyun clock-names = "core", "iface"; 51*4882a593Smuzhiyun dmas = <&dma0 0>, <&dma0 1>; 52*4882a593Smuzhiyun dma-names = "tx", "rx"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun- A uartdm v1.3 device without dma capabilities and part of a GSBI complex. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun serial@19c40000 { 58*4882a593Smuzhiyun compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 59*4882a593Smuzhiyun reg = <0x19c40000 0x1000>, 60*4882a593Smuzhiyun <0x19c00000 0x1000>; 61*4882a593Smuzhiyun interrupts = <0 195 0x0>; 62*4882a593Smuzhiyun clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; 63*4882a593Smuzhiyun clock-names = "core", "iface"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun- serialN alias. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun aliases { 69*4882a593Smuzhiyun serial0 = &uarta; 70*4882a593Smuzhiyun serial1 = &uartc; 71*4882a593Smuzhiyun serial2 = &uartb; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun uarta: serial@12490000 { 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun uartb: serial@16340000 { 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun uartc: serial@1a240000 { 81*4882a593Smuzhiyun }; 82