1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/serial/pl011.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM AMBA Primecell PL011 serial UART 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Rob Herring <robh@kernel.org> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: /schemas/serial.yaml# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun# Need a custom select here or 'arm,primecell' will match on lots of nodes 16*4882a593Smuzhiyunselect: 17*4882a593Smuzhiyun properties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun contains: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - arm,pl011 22*4882a593Smuzhiyun - zte,zx296702-uart 23*4882a593Smuzhiyun required: 24*4882a593Smuzhiyun - compatible 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunproperties: 27*4882a593Smuzhiyun compatible: 28*4882a593Smuzhiyun oneOf: 29*4882a593Smuzhiyun - items: 30*4882a593Smuzhiyun - const: arm,pl011 31*4882a593Smuzhiyun - const: arm,primecell 32*4882a593Smuzhiyun - items: 33*4882a593Smuzhiyun - const: zte,zx296702-uart 34*4882a593Smuzhiyun - const: arm,primecell 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reg: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun interrupts: 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun pinctrl-0: true 43*4882a593Smuzhiyun pinctrl-1: true 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pinctrl-names: 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun When present, must have one state named "default", 48*4882a593Smuzhiyun and may contain a second name named "sleep". The former 49*4882a593Smuzhiyun state sets up pins for ordinary operation whereas 50*4882a593Smuzhiyun the latter state will put the associated pins to sleep 51*4882a593Smuzhiyun when the UART is unused 52*4882a593Smuzhiyun minItems: 1 53*4882a593Smuzhiyun items: 54*4882a593Smuzhiyun - const: default 55*4882a593Smuzhiyun - const: sleep 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun clocks: 58*4882a593Smuzhiyun description: 59*4882a593Smuzhiyun When present, the first clock listed must correspond to 60*4882a593Smuzhiyun the clock named UARTCLK on the IP block, i.e. the clock 61*4882a593Smuzhiyun to the external serial line, whereas the second clock 62*4882a593Smuzhiyun must correspond to the PCLK clocking the internal logic 63*4882a593Smuzhiyun of the block. Just listing one clock (the first one) is 64*4882a593Smuzhiyun deprecated. 65*4882a593Smuzhiyun maxItems: 2 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clock-names: 68*4882a593Smuzhiyun items: 69*4882a593Smuzhiyun - const: uartclk 70*4882a593Smuzhiyun - const: apb_pclk 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dmas: 73*4882a593Smuzhiyun minItems: 1 74*4882a593Smuzhiyun maxItems: 2 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun dma-names: 77*4882a593Smuzhiyun minItems: 1 78*4882a593Smuzhiyun items: 79*4882a593Smuzhiyun - const: rx 80*4882a593Smuzhiyun - const: tx 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun auto-poll: 83*4882a593Smuzhiyun description: 84*4882a593Smuzhiyun Enables polling when using RX DMA. 85*4882a593Smuzhiyun type: boolean 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun poll-rate-ms: 88*4882a593Smuzhiyun description: 89*4882a593Smuzhiyun Rate at which poll occurs when auto-poll is set. 90*4882a593Smuzhiyun default 100ms. 91*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 92*4882a593Smuzhiyun default: 100 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun poll-timeout-ms: 95*4882a593Smuzhiyun description: 96*4882a593Smuzhiyun Poll timeout when auto-poll is set, default 97*4882a593Smuzhiyun 3000ms. 98*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 99*4882a593Smuzhiyun default: 3000 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunrequired: 102*4882a593Smuzhiyun - compatible 103*4882a593Smuzhiyun - reg 104*4882a593Smuzhiyun - interrupts 105*4882a593Smuzhiyun 106*4882a593Smuzhiyundependencies: 107*4882a593Smuzhiyun poll-rate-ms: [ auto-poll ] 108*4882a593Smuzhiyun poll-timeout-ms: [ auto-poll ] 109*4882a593Smuzhiyun 110*4882a593SmuzhiyunadditionalProperties: false 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunexamples: 113*4882a593Smuzhiyun - | 114*4882a593Smuzhiyun serial@80120000 { 115*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 116*4882a593Smuzhiyun reg = <0x80120000 0x1000>; 117*4882a593Smuzhiyun interrupts = <0 11 4>; 118*4882a593Smuzhiyun dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; 119*4882a593Smuzhiyun dma-names = "rx", "tx"; 120*4882a593Smuzhiyun clocks = <&foo_clk>, <&bar_clk>; 121*4882a593Smuzhiyun clock-names = "uartclk", "apb_pclk"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun... 125