1*4882a593SmuzhiyunOMAP UART controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers 5*4882a593Smuzhiyun- compatible : should be "ti,am654-uart" for AM654 controllers 6*4882a593Smuzhiyun- compatible : should be "ti,omap2-uart" for OMAP2 controllers 7*4882a593Smuzhiyun- compatible : should be "ti,omap3-uart" for OMAP3 controllers 8*4882a593Smuzhiyun- compatible : should be "ti,omap4-uart" for OMAP4 controllers 9*4882a593Smuzhiyun- compatible : should be "ti,am4372-uart" for AM437x controllers 10*4882a593Smuzhiyun- compatible : should be "ti,am3352-uart" for AM335x controllers 11*4882a593Smuzhiyun- compatible : should be "ti,dra742-uart" for DRA7x controllers 12*4882a593Smuzhiyun- reg : address and length of the register space 13*4882a593Smuzhiyun- interrupts or interrupts-extended : Should contain the uart interrupt 14*4882a593Smuzhiyun specifier or both the interrupt 15*4882a593Smuzhiyun controller phandle and interrupt 16*4882a593Smuzhiyun specifier. 17*4882a593Smuzhiyun- ti,hwmods : Must be "uart<n>", n being the instance number (1-based) 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- clock-frequency : frequency of the clock input to the UART 21*4882a593Smuzhiyun- dmas : DMA specifier, consisting of a phandle to the DMA controller 22*4882a593Smuzhiyun node and a DMA channel number. 23*4882a593Smuzhiyun- dma-names : "rx" for receive channel, "tx" for transmit channel. 24*4882a593Smuzhiyun- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt 25*4882a593Smuzhiyun- rs485-rts-active-high: drive RTS high when sending (default is low). 26*4882a593Smuzhiyun- clocks: phandle to the functional clock as per 27*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uart4: serial@49042000 { 32*4882a593Smuzhiyun compatible = "ti,omap3-uart"; 33*4882a593Smuzhiyun reg = <0x49042000 0x400>; 34*4882a593Smuzhiyun interrupts = <80>; 35*4882a593Smuzhiyun dmas = <&sdma 81 &sdma 82>; 36*4882a593Smuzhiyun dma-names = "tx", "rx"; 37*4882a593Smuzhiyun ti,hwmods = "uart4"; 38*4882a593Smuzhiyun clock-frequency = <48000000>; 39*4882a593Smuzhiyun }; 40