1*4882a593Smuzhiyun* NXP LPC1850 UART 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "nxp,lpc1850-uart", "ns16550a". 5*4882a593Smuzhiyun- reg : offset and length of the register set for the device. 6*4882a593Smuzhiyun- interrupts : should contain uart interrupt. 7*4882a593Smuzhiyun- clocks : phandle to the input clocks. 8*4882a593Smuzhiyun- clock-names : required elements: "uartclk", "reg". 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties: 11*4882a593Smuzhiyun- dmas : Two or more DMA channel specifiers following the 12*4882a593Smuzhiyun convention outlined in bindings/dma/dma.txt 13*4882a593Smuzhiyun- dma-names : Names for the dma channels, if present. There must 14*4882a593Smuzhiyun be at least one channel named "tx" for transmit 15*4882a593Smuzhiyun and named "rx" for receive. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunSince it's also possible to also use the of_serial.c driver all 18*4882a593Smuzhiyunparameters from 8250.txt also apply but are optional. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyunuart0: serial@40081000 { 22*4882a593Smuzhiyun compatible = "nxp,lpc1850-uart", "ns16550a"; 23*4882a593Smuzhiyun reg = <0x40081000 0x1000>; 24*4882a593Smuzhiyun reg-shift = <2>; 25*4882a593Smuzhiyun interrupts = <24>; 26*4882a593Smuzhiyun clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 27*4882a593Smuzhiyun clock-names = "uartclk", "reg"; 28*4882a593Smuzhiyun}; 29