1*4882a593SmuzhiyunNVIDIA Tegra Combined UART (TCU) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe TCU is a system for sharing a hardware UART instance among multiple 4*4882a593Smuzhiyunsystems within the Tegra SoC. It is implemented through a mailbox- 5*4882a593Smuzhiyunbased protocol where each "virtual UART" has a pair of mailboxes, one 6*4882a593Smuzhiyunfor transmitting and one for receiving, that is used to communicate 7*4882a593Smuzhiyunwith the hardware implementing the TCU. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- name : Should be tcu 11*4882a593Smuzhiyun- compatible 12*4882a593Smuzhiyun Array of strings 13*4882a593Smuzhiyun One of: 14*4882a593Smuzhiyun - "nvidia,tegra194-tcu" 15*4882a593Smuzhiyun- mbox-names: 16*4882a593Smuzhiyun "rx" - Mailbox for receiving data from hardware UART 17*4882a593Smuzhiyun "tx" - Mailbox for transmitting data to hardware UART 18*4882a593Smuzhiyun- mboxes: Mailboxes corresponding to the mbox-names. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThis node is a mailbox consumer. See the following files for details of 21*4882a593Smuzhiyunthe mailbox subsystem, and the specifiers implemented by the relevant 22*4882a593Smuzhiyunprovider(s): 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- .../mailbox/mailbox.txt 25*4882a593Smuzhiyun- .../mailbox/nvidia,tegra186-hsp.txt 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample bindings: 28*4882a593Smuzhiyun----------------- 29*4882a593Smuzhiyun 30*4882a593Smuzhiyuntcu: tcu { 31*4882a593Smuzhiyun compatible = "nvidia,tegra194-tcu"; 32*4882a593Smuzhiyun mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, 33*4882a593Smuzhiyun <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; 34*4882a593Smuzhiyun mbox-names = "rx", "tx"; 35*4882a593Smuzhiyun}; 36