1*4882a593SmuzhiyunNVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be, 5*4882a593Smuzhiyun "nvidia,tegra20-hsuart" for Tegra20, 6*4882a593Smuzhiyun "nvidia,tegra30-hsuart" for Tegra30, 7*4882a593Smuzhiyun "nvidia,tegra186-hsuart" for Tegra186, 8*4882a593Smuzhiyun "nvidia,tegra194-hsuart" for Tegra194. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- reg: Should contain UART controller registers location and length. 11*4882a593Smuzhiyun- interrupts: Should contain UART controller interrupts. 12*4882a593Smuzhiyun- clocks: Must contain one entry, for the module clock. 13*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 14*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 15*4882a593Smuzhiyun See ../reset/reset.txt for details. 16*4882a593Smuzhiyun- reset-names : Must include the following entries: 17*4882a593Smuzhiyun - serial 18*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in dma-names. 19*4882a593Smuzhiyun See ../dma/dma.txt for details. 20*4882a593Smuzhiyun- dma-names : Must include the following entries: 21*4882a593Smuzhiyun - rx 22*4882a593Smuzhiyun - tx 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable 26*4882a593Smuzhiyun only if all 8 lines of UART controller are pinmuxed. 27*4882a593Smuzhiyun- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate 28*4882a593Smuzhiyun adjustment within a range. 29*4882a593Smuzhiyun Each entry contains sets of 3 values. Range low/high and adjusted rate. 30*4882a593Smuzhiyun <range_low range_high adjusted_rate> 31*4882a593Smuzhiyun When baud rate set on controller falls within the range mentioned in this 32*4882a593Smuzhiyun field, baud rate will be adjusted by percentage mentioned here. 33*4882a593Smuzhiyun Ex: <9600 115200 200> 34*4882a593Smuzhiyun Increase baud rate by 2% when set baud rate falls within range 9600 to 115200 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunBaud Rate tolerance: 37*4882a593Smuzhiyun Standard UART devices are expected to have tolerance for baud rate error by 38*4882a593Smuzhiyun -4 to +4 %. All Tegra devices till Tegra210 had this support. However, 39*4882a593Smuzhiyun Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level 40*4882a593Smuzhiyun is 0% to +4% in 1-stop config. Otherwise, the received data will have 41*4882a593Smuzhiyun corruption/invalid framing errors. Parker errata suggests adjusting baud 42*4882a593Smuzhiyun rate to be higher than the deviations observed in Tx. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun Tx deviation of connected device can be captured over scope (or noted from 45*4882a593Smuzhiyun its spec) for valid range and Tegra baud rate has to be set above actual 46*4882a593Smuzhiyun Tx baud rate observed. To do this we use nvidia,adjust-baud-rates 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun As an example, consider there is deviation observed in Tx for baud rates as 49*4882a593Smuzhiyun listed below. 50*4882a593Smuzhiyun 0 to 9600 has 1% deviation 51*4882a593Smuzhiyun 9600 to 115200 2% deviation 52*4882a593Smuzhiyun This slight deviation is expcted and Tegra UART is expected to handle it. Due 53*4882a593Smuzhiyun to the issue stated above, baud rate on Tegra UART should be set equal to or 54*4882a593Smuzhiyun above deviation observed for avoiding frame errors. 55*4882a593Smuzhiyun Property should be set like this 56*4882a593Smuzhiyun nvidia,adjust-baud-rates = <0 9600 100>, 57*4882a593Smuzhiyun <9600 115200 200>; 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunExample: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunserial@70006000 { 62*4882a593Smuzhiyun compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; 63*4882a593Smuzhiyun reg = <0x70006000 0x40>; 64*4882a593Smuzhiyun reg-shift = <2>; 65*4882a593Smuzhiyun interrupts = <0 36 0x04>; 66*4882a593Smuzhiyun nvidia,enable-modem-interrupt; 67*4882a593Smuzhiyun clocks = <&tegra_car 6>; 68*4882a593Smuzhiyun resets = <&tegra_car 6>; 69*4882a593Smuzhiyun reset-names = "serial"; 70*4882a593Smuzhiyun dmas = <&apbdma 8>, <&apbdma 8>; 71*4882a593Smuzhiyun dma-names = "rx", "tx"; 72*4882a593Smuzhiyun nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */ 73*4882a593Smuzhiyun}; 74